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Speedups, Bug Fixes, Series Device

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@PetePupalaikis PetePupalaikis released this 23 May 23:51

This release adds some speedups, fixes a few bugs, and adds a series device

Bug Fixes

Cache Recalculation

An error was found that projects sometimes required recalculation of the cached solution, even if they had already been calculated. This bug was not commonly encountered by users and happened only for scripted solutions.

All of the tests were fixed, as well.

Features

Allow Archiving of Cached Results

When archiving, cached results can be archived as well (selectable in the preferences). Unfortunately, due to some limitations in Python, these cached results will need recalculation, unless the archive is extracted using a utility, rather than SignalIntegrity. This will be resolved in the future.

Series Device

A multi-port (even number of ports) device can be dropped into a schematic that calculates the cascade multiple times of a referenced project or s-parameter file. This is useful for converting transmission line models (that might not exactly fit the RLGC paradigm) into distributed models.

Speedups

Since SignalIntegrity is currently being used for some very large simulations, efforts were made to profile and reduce wasted time in the calculations. These are for simulations and s-parameter generation.