😃
Electrical & Electronic Engineering Undergraduate
-
RMIT University VN
- Ho Chi Minh City, VN
- www.linkedin.com/in/tkminh911
Highlights
- Pro
Block or Report
Block or report MinhTran0911
Report abuse
Contact GitHub support about this user’s behavior. Learn more about reporting abuse.
Report abusePopular repositories
-
DS1302_Interface_DE10
DS1302_Interface_DE10 PublicDS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
SystemVerilog 1
-
Key_Matrix_3x3_NUC140
Key_Matrix_3x3_NUC140 Public3x3 Key Matrix for Nuvoton NuMicro NUC140 Microcontroller
C
-
DS1302_Interface_ATmega328P
DS1302_Interface_ATmega328P PublicDS1302 Real-time Clock (RTC) module Interfacing with Microchip ATmega328P Microcontroller
C 1
-
Traffic_Light_Controller_ATmega328P
Traffic_Light_Controller_ATmega328P PublicTraffic Light Controller with Microchip ATmega328P Microcontroller
C
-
Simple_CPU_DE10
Simple_CPU_DE10 PublicSimple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA
SystemVerilog
-
Stopwatch_DE10
Stopwatch_DE10 PublicBasic Stopwatch Design using Terasic DE-10 Standard FPGA
SystemVerilog
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.