i#5623: AARCH64 feature FEAT_PAUTH2 is now recognized #6808
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Enhance the AARCH64 feature interface so that we can correctly identify features identifed by more than one register nibble. Update the identification of FEATURE_PAUTH so that all six identification nibbles are checked. Remove the automatic assumption that if the value of the nibble in the register is greater than the expected value then the feature is implemented. Issue: #5623
AssadHashmi
requested changes
May 13, 2024
Adds a very simple histogram with fixed bin sizes recording the distribution of instructions per context switch in the schedule_stats tool. Updates two tests to confirm the histogram is produced. This feature is structured to allow replacing this simple histogram with a more sophisticated version in subclasses. Issue: #6426
…ort (#6810) This is the first part of adding RISC-V vector (RVV) extension support to the core. RVV is a vector architecture similar to SVE, and its vector length (VLEN) can vary from 64 up to 65536. For more information about RVV, please refer to https://github.com/riscv/riscv-isa-manual. The code itself is compiled and preliminarily tested on real hardware with RVV (VLEN=256) support by running https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/main/examples/rvv_strlen.c. isl/v.txt is transformed from https://github.com/riscv/riscv-opcodes/blob/master/rv_v by an off-tree one-time python script. Follow-up patches will address the following parts with RVV support: - encoder/decoder unit tests; - code cache context switch; - clean-call; - signal context; - scatter/gather emulation; - sample clients and dr$sim; - and maybe more. Issue: #3544
Add ldg to the list of opcodes which are excluded from instr_reads_memory() and add a similar mechanism to exclude stg/st2g from instr_writes_memory(). These instructions have a similar operand signature to load/store instructions but they actually read/write allocation tags for the pointer indicated by the memory operand, rather than read/write the memory it points to. Issue: #6796 Fixes: #6796
derekbruening
approved these changes
May 17, 2024
AssadHashmi
approved these changes
May 20, 2024
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Enhance the AARCH64 feature interface so that we can correctly identify features identifed by more than one register nibble.
Update the identification of FEATURE_PAUTH so that all six identification nibbles are checked.
Remove the automatic assumption that if the value of the nibble in the register is greater than the expected value then the feature is implemented.
Issue: #5623