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16bit_shift_adder
16bit_shift_adder PublicProject to Design and Implement a 16-bit Shift Adder (Serial Adder) using Verilog.
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16bit_barrel_shifter
16bit_barrel_shifter PublicProject to Design and Implement a 16-bit Barrel Shifter using Verilog.
Verilog 2
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Twitter_Scraping
Twitter_Scraping PublicScraping Tweets from Twitter using twint, kafka, CMAK and MongoDB
Python
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TSF_GRIP-IPL_EDA
TSF_GRIP-IPL_EDA PublicExploratory Data Analysis on the IPL dataset collected from 2008-2019 as part of the TSF - GRIP.
Jupyter Notebook
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