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Rowan University
- Glassboro, New Jersey, USA
- in/soham-bhattacharya-026187143
- https://www.researchgate.net/profile/Soham-Bhattacharya-3
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Verilog-Tutorial-for-Beginners
Verilog-Tutorial-for-Beginners PublicThis is "In Progress" Repo for all the beginners who want to learn Digital Design using Verilog HDL.
Verilog
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RISCV-HDP
RISCV-HDP PublicHardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)
Verilog
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Euler-and-Modified-Euler-Hardware-Accelerator
Euler-and-Modified-Euler-Hardware-Accelerator PublicHardware Accelerator design for Euler and Modified method in solving ODE using VHDL language in Xilinx Vivado Environment
VHDL
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Implementation-of-Runge-Kutta-Hardware-Accelerator
Implementation-of-Runge-Kutta-Hardware-Accelerator PublicHardware Accelerator implementation for solving an ordinary differential equation using Runge Kutta Numerical methods using VHDL language
VHDL
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chisel_tutorial
chisel_tutorial PublicForked from chipsalliance/chisel
Chisel: A Modern Hardware Design Language
Scala
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Half-Precision-RK-Accelerator
Half-Precision-RK-Accelerator PublicHardware Accelerator For Runge-Kutta solvers for ODE using Half Precision Floating Point Unit
VHDL
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