riscv_vt52

A single verilog file that crams vt52-fpga, picosoc (from the tinyfpga bx repository), and verilog-uart into one verilog wrapper.

Name		Name	Last commit message	Last commit date
Latest commit History 19 Commits
mem		mem
tinyfpga_bx_usbserial		tinyfpga_bx_usbserial
LICENSE		LICENSE
Makefile		Makefile
README.md		README.md
UART_AUTHORS		UART_AUTHORS
UART_README.md		UART_README.md
char_buffer.v		char_buffer.v
char_rom.v		char_rom.v
clock_constraints.py		clock_constraints.py
clock_generator.v		clock_generator.v
command_handler.v		command_handler.v
cursor.v		cursor.v
cursor_blinker.v		cursor_blinker.v
custom_ops.S		custom_ops.S
firmware.c		firmware.c
hardware.pcf		hardware.pcf
hardware.v		hardware.v
keyboard.v		keyboard.v
keymap_rom.v		keymap_rom.v
picorv32.v		picorv32.v
picosoc.v		picosoc.v
pll.v		pll.v
riscv_flash.ld		riscv_flash.ld
sections.lds		sections.lds
simple_register.v		simple_register.v
simpleuart.v		simpleuart.v
spiflash.v		spiflash.v
spimemio.v		spimemio.v
start.S		start.S
uart.v		uart.v
uart_rx.v		uart_rx.v
uart_tx.v		uart_tx.v
video_generator.v		video_generator.v
vt52.v		vt52.v
vt52_README.md		vt52_README.md

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