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Getting a module parameter using scope resolution operator #4890

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ba-sc opened this issue Feb 11, 2024 · 6 comments · May be fixed by #4906
Open

Getting a module parameter using scope resolution operator #4890

ba-sc opened this issue Feb 11, 2024 · 6 comments · May be fixed by #4906
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area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800

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@ba-sc
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ba-sc commented Feb 11, 2024

Hello!

By using the scope resolution operator (::) we can access the default parameters from the module definition, which, as far as I understand, is not allowed.

IEEE 1800-2017:

Screenshot from 2024-02-11 22-23-16

Run example on VCS:

Error-[SV-LCM-PND] Package not defined
tb.sv, 9
tb, "my_module"
  Package scope resolution failed. Token 'my_module' is not a package. 
  Originating module 'tb'.
  Move package definition before the use of the package.

Run example on Xcelium:

  localparam integer NUMBERS = my_module::PARAM;
                                       |
xmvlog: *E,NOPBIND (tb.sv,9|39): Package my_module could not be bound.

Can you attach an example that shows the issue?

/* verilator lint_off MULTITOP */

module my_module #(
  integer PARAM = 123
);
endmodule

module tb;
  localparam integer NUMBERS = my_module::PARAM;

  initial begin
    $display(NUMBERS);
    $finish();
  end
endmodule

Output:

        123
- tb.sv:13: Verilog $finish

What 'verilator' command line do we use to run your example?

verilator --binary -j 0 tb.sv
obj_dir/Vtb

What 'verilator --version' are you using? Did you try it with the git master version?

Verilator 5.021 devel rev v5.020-101-gcbc76a781

Yes, this is git master.

What OS and distribution are you using?

Ubuntu 22.04.3 (GitHub Codespaces: Verilator Devcontainer)
@ba-sc ba-sc added the new New issue not seen by maintainers label Feb 11, 2024
@wsnyder
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wsnyder commented Feb 11, 2024

Makes sense, the code isn't checking it's a parameter when resolving.

Might you be willing to make a pull request with the fix, test case, and .out file to check the new error message?

@wsnyder wsnyder added area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800 and removed new New issue not seen by maintainers labels Feb 11, 2024
@ba-sc
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ba-sc commented Feb 13, 2024

Might you be willing to make a pull request with the fix, test case, and .out file to check the new error message?

Yes, I would like to do this. Are there any deadlines?

@wsnyder
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wsnyder commented Feb 13, 2024

When you get a chance. We release every 2 months or so.

@wsnyder
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wsnyder commented Feb 13, 2024

(We won't wait for it, just saying in case you want it out there.)

@ba-sc
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ba-sc commented Feb 13, 2024

Ok, thanks! I'll take it on and open a PR when I have something to show.

@ba-sc ba-sc linked a pull request Feb 19, 2024 that will close this issue
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@ba-sc
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ba-sc commented Feb 19, 2024

Something else. If you specify the top module

verilator --binary -j 0 -top tb tb.sv

, then we get an internal error

%Error: Internal Error: tb.sv:3:8: ../V3LinkDot.cpp:422: Module/etc never assigned a symbol entry?
    3 | module my_module #(
      |        ^~~~~~~~~
                        ... See the manual at https://verilator.org/verilator_doc.html for more assistance.

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area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned' type: feature-IEEE Request to add new feature, described in IEEE 1800
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Fix scope resolution operator working with module/interface (#4890) ba-sc/verilator
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@wsnyder @ba-sc