lora_tx.ldf

<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="lora_tx" device="LFE5U-25F-6BG256I" default_implementation="impl1">
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    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
        <Options def_top="topModule" top="topModule"/>
        <Source name="source/rtl/accInc.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="source/rtl/chirpGenerator.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="source/rtl/clockDivider.v" type="Verilog" type_short="Verilog">
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        <Source name="source/rtl/constant.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="source/rtl/cosIdeal.v" type="Verilog" type_short="Verilog">
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        </Source>
        <Source name="source/rtl/counter.v" type="Verilog" type_short="Verilog">
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        <Source name="source/rtl/DEDFF.v" type="Verilog" type_short="Verilog">
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        </Source>
        <Source name="source/rtl/initialPhase.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="source/rtl/IQSerializer.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="source/rtl/loRaModulator.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="source/rtl/loraPacketGenerator.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="source/rtl/LoRaTXDefines.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="source/rtl/phaseInc.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="source/rtl/radioDefines.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="source/rtl/sinIdeal.v" type="Verilog" type_short="Verilog">
            <Options/>
        </Source>
        <Source name="source/rtl/topModule.v" type="Verilog" type_short="Verilog">
            <Options top_module="topModule"/>
        </Source>
        <Source name="project/lora_tx_clarity/lora_tx_clarity.sbx" type="sbx" type_short="SBX">
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        </Source>
        <Source name="impl1/Untitled.pcf" type="Power Calculator" type_short="PCF" excluded="TRUE">
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        </Source>
        <Source name="project/flash.xcf" type="Programming Project File" type_short="Programming">
            <Options/>
        </Source>
        <Source name="source/lora_modulator.lpf" type="Logic Preference" type_short="LPF">
            <Options/>
        </Source>
    </Implementation>
    <Strategy name="Strategy1" file="project/lora_tx.sty"/>
</BaliProject>