You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
You have done great work!
Could you please share with us the TCL script used/generated from the FPGA run?
And maybe more details on building the image and FPGA run flow?
Thanks a lot,
Alaa
The text was updated successfully, but these errors were encountered:
Hello,
Has the FPGA been able to run?,
second, how have you loaded initialized memory from verilog file?
Thanks,
Emilio
Hello,
You have done great work!
Could you please share with us the TCL script used/generated from the FPGA run?
And maybe more details on building the image and FPGA run flow?
Hello,
You have done great work!
Could you please share with us the TCL script used/generated from the FPGA run?
And maybe more details on building the image and FPGA run flow?
Thanks a lot,
Alaa
The text was updated successfully, but these errors were encountered: