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USRPDevice.cpp.patch
101 lines (92 loc) · 4.12 KB
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USRPDevice.cpp.patch
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--- USRPDevice.cpp 2010-07-17 07:01:45.000000000 +0700
+++ USRPDevice.cpp.new 2011-04-15 23:17:59.000000000 +0700
@@ -59,7 +59,13 @@ bool USRPDevice::compute_regs(double fre
unsigned *N,
double *actual_freq)
{
-
+ if (freq < 1.2e9) {
+ DIV2 = 1;
+ freq_mult = 2;
+ } else {
+ DIV2 = 0;
+ freq_mult =1;
+ }
float phdet_freq = 64.0e6/R_DIV;
int desired_n = (int) round(freq*freq_mult/phdet_freq);
*actual_freq = desired_n * phdet_freq/freq_mult;
@@ -122,17 +128,17 @@ bool USRPDevice::rx_setFreq(double freq,
if (!compute_regs(freq, &R, &control, &N, actual_freq)) return false;
if (R==0) return false;
- m_uRx->_write_spi(0,SPI_ENABLE_RX_B,SPI_FMT_MSB | SPI_FMT_HDR_0,
+ m_uRx->_write_spi(0,SPI_ENABLE_RX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
write_it((R & ~0x3) | 1));
- m_uRx->_write_spi(0,SPI_ENABLE_RX_B,SPI_FMT_MSB | SPI_FMT_HDR_0,
+ m_uRx->_write_spi(0,SPI_ENABLE_RX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
write_it((control & ~0x3) | 0));
usleep(10000);
- m_uRx->_write_spi(0,SPI_ENABLE_RX_B,SPI_FMT_MSB | SPI_FMT_HDR_0,
+ m_uRx->_write_spi(0,SPI_ENABLE_RX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
write_it((N & ~0x3) | 2));
- if (m_uRx->read_io(1) & PLL_LOCK_DETECT) return true;
- if (m_uRx->read_io(1) & PLL_LOCK_DETECT) return true;
+ if (m_uRx->read_io(0) & PLL_LOCK_DETECT) return true;
+ if (m_uRx->read_io(0) & PLL_LOCK_DETECT) return true;
return false;
}
@@ -232,33 +238,31 @@ bool USRPDevice::start()
// power up and configure daughterboards
m_uTx->_write_oe(0,0,0xffff);
m_uTx->_write_oe(0,(POWER_UP|RX_TXN|ENABLE), 0xffff);
- m_uTx->write_io(0,(~POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
- m_uTx->write_io(0,ENABLE,(RX_TXN | ENABLE));
+ m_uTx->write_io(0, ENABLE, ENABLE | RX_TXN | POWER_UP); /* power up inverted */
m_uTx->_write_fpga_reg(FR_ATR_MASK_0 ,0);//RX_TXN|ENABLE);
m_uTx->_write_fpga_reg(FR_ATR_TXVAL_0,0);//,0 |ENABLE);
m_uTx->_write_fpga_reg(FR_ATR_RXVAL_0,0);//,RX_TXN|0);
m_uTx->_write_fpga_reg(40,0);
m_uTx->_write_fpga_reg(42,0);
- m_uTx->set_pga(0,m_uTx->pga_max()); // should be 20dB
- m_uTx->set_pga(1,m_uTx->pga_max());
+ m_uTx->set_pga(0,m_uTx->pga_min()); // should be 20dB
+ m_uTx->set_pga(1,m_uTx->pga_min());
m_uTx->set_mux(0x00000098);
- LOG(INFO) << "TX pgas: " << m_uTx->pga(0) << ", " << m_uTx->pga(1);
if (!skipRx) {
- m_uRx->_write_fpga_reg(FR_ATR_MASK_0 + 3*3,0);
- m_uRx->_write_fpga_reg(FR_ATR_TXVAL_0 + 3*3,0);
- m_uRx->_write_fpga_reg(FR_ATR_RXVAL_0 + 3*3,0);
+ m_uRx->_write_fpga_reg(FR_ATR_MASK_0 + 1*3,0);
+ m_uRx->_write_fpga_reg(FR_ATR_TXVAL_0 + 1*3,0);
+ m_uRx->_write_fpga_reg(FR_ATR_RXVAL_0 + 1*3,0);
+ m_uRx->_write_fpga_reg(41,0);
m_uRx->_write_fpga_reg(43,0);
- m_uRx->_write_oe(1,(POWER_UP|RX_TXN|ENABLE), 0xffff);
- m_uRx->write_io(1,(~POWER_UP|RX_TXN|ENABLE),(POWER_UP|RX_TXN|ENABLE));
- //m_uRx->write_io(1,0,RX2_RX1N); // using Tx/Rx/
- m_uRx->write_io(1,RX2_RX1N,RX2_RX1N); // using Rx2
- m_uRx->set_adc_buffer_bypass(2,true);
- m_uRx->set_adc_buffer_bypass(3,true);
- m_uRx->set_pga(2,m_uRx->pga_max()); // should be 20dB
- m_uRx->set_pga(3,m_uRx->pga_max());
- m_uRx->set_mux(0x00000032);
- m_uRx->write_aux_dac(1,0,(int) ceil(0.2*4096.0/3.3)); // set to maximum gain
+ m_uRx->_write_oe(0,0,0xffff);
+ m_uRx->_write_oe(0,(POWER_UP|RX2_RX1N|ENABLE), 0xffff);
+ m_uRx->write_io(0, ENABLE | RX2_RX1N, ENABLE | RX2_RX1N | POWER_UP); /* power up inverted */
+ m_uRx->set_adc_buffer_bypass(0,true);
+ m_uRx->set_adc_buffer_bypass(1,true);
+ m_uRx->set_pga(0,m_uRx->pga_max()); // should be 20dB
+ m_uRx->set_pga(1,m_uRx->pga_max());
+ m_uRx->set_mux(0x00000010);
+ m_uRx->write_aux_dac(0,0,(int) ceil(0.2*4096.0/3.3)); // set to maximum gain
}
data = new short[currDataSize];
@@ -291,8 +295,8 @@ bool USRPDevice::stop()
if (!m_uTx) return false;
// power down
- m_uTx->write_io(0,(~POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
- m_uRx->write_io(1,~POWER_UP,(POWER_UP|ENABLE));
+ m_uTx->write_io(0, POWER_UP, (POWER_UP|ENABLE));
+ m_uRx->write_io(0, POWER_UP, (POWER_UP|ENABLE));
delete[] currData;