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bnx2x_ethtool.c
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/* bnx2x_ethtool.c: QLogic Everest network driver.
*
* Copyright (c) 2007-2013 Broadcom Corporation
* Copyright (c) 2014 QLogic Corporation
* All rights reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation.
*
* Maintained by: Ariel Elior <[email protected]>
* Written by: Eliezer Tamir
* Based on code from Michael Chan's bnx2 driver
* UDP CSUM errata workaround by Arik Gendelman
* Slowpath and fastpath rework by Vladislav Zolotarov
* Statistics and Link management by Yitchak Gertner
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/ethtool.h>
#include <linux/netdevice.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/crc32.h>
#include "bnx2x.h"
#include "bnx2x_cmn.h"
#include "bnx2x_dump.h"
#include "bnx2x_init.h"
/* Note: in the format strings below %s is replaced by the queue-name which is
* either its index or 'fcoe' for the fcoe queue. Make sure the format string
* length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
*/
#define MAX_QUEUE_NAME_LEN 4
static const struct {
long offset;
int size;
char string[ETH_GSTRING_LEN];
} bnx2x_q_stats_arr[] = {
/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
{ Q_STATS_OFFSET32(total_unicast_packets_received_hi),
8, "[%s]: rx_ucast_packets" },
{ Q_STATS_OFFSET32(total_multicast_packets_received_hi),
8, "[%s]: rx_mcast_packets" },
{ Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
8, "[%s]: rx_bcast_packets" },
{ Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
{ Q_STATS_OFFSET32(rx_err_discard_pkt),
4, "[%s]: rx_phy_ip_err_discards"},
{ Q_STATS_OFFSET32(rx_skb_alloc_failed),
4, "[%s]: rx_skb_alloc_discard" },
{ Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
{ Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" },
{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
8, "[%s]: tx_ucast_packets" },
{ Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
8, "[%s]: tx_mcast_packets" },
{ Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
8, "[%s]: tx_bcast_packets" },
{ Q_STATS_OFFSET32(total_tpa_aggregations_hi),
8, "[%s]: tpa_aggregations" },
{ Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
8, "[%s]: tpa_aggregated_frames"},
{ Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
{ Q_STATS_OFFSET32(driver_filtered_tx_pkt),
4, "[%s]: driver_filtered_tx_pkt" }
};
#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
static const struct {
long offset;
int size;
bool is_port_stat;
char string[ETH_GSTRING_LEN];
} bnx2x_stats_arr[] = {
/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
8, false, "rx_bytes" },
{ STATS_OFFSET32(error_bytes_received_hi),
8, false, "rx_error_bytes" },
{ STATS_OFFSET32(total_unicast_packets_received_hi),
8, false, "rx_ucast_packets" },
{ STATS_OFFSET32(total_multicast_packets_received_hi),
8, false, "rx_mcast_packets" },
{ STATS_OFFSET32(total_broadcast_packets_received_hi),
8, false, "rx_bcast_packets" },
{ STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
8, true, "rx_crc_errors" },
{ STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
8, true, "rx_align_errors" },
{ STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
8, true, "rx_undersize_packets" },
{ STATS_OFFSET32(etherstatsoverrsizepkts_hi),
8, true, "rx_oversize_packets" },
/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
8, true, "rx_fragments" },
{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
8, true, "rx_jabbers" },
{ STATS_OFFSET32(no_buff_discard_hi),
8, false, "rx_discards" },
{ STATS_OFFSET32(mac_filter_discard),
4, true, "rx_filtered_packets" },
{ STATS_OFFSET32(mf_tag_discard),
4, true, "rx_mf_tag_discard" },
{ STATS_OFFSET32(pfc_frames_received_hi),
8, true, "pfc_frames_received" },
{ STATS_OFFSET32(pfc_frames_sent_hi),
8, true, "pfc_frames_sent" },
{ STATS_OFFSET32(brb_drop_hi),
8, true, "rx_brb_discard" },
{ STATS_OFFSET32(brb_truncate_hi),
8, true, "rx_brb_truncate" },
{ STATS_OFFSET32(pause_frames_received_hi),
8, true, "rx_pause_frames" },
{ STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
8, true, "rx_mac_ctrl_frames" },
{ STATS_OFFSET32(nig_timer_max),
4, true, "rx_constant_pause_events" },
/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
4, false, "rx_phy_ip_err_discards"},
{ STATS_OFFSET32(rx_skb_alloc_failed),
4, false, "rx_skb_alloc_discard" },
{ STATS_OFFSET32(hw_csum_err),
4, false, "rx_csum_offload_errors" },
{ STATS_OFFSET32(driver_xoff),
4, false, "tx_exhaustion_events" },
{ STATS_OFFSET32(total_bytes_transmitted_hi),
8, false, "tx_bytes" },
{ STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
8, true, "tx_error_bytes" },
{ STATS_OFFSET32(total_unicast_packets_transmitted_hi),
8, false, "tx_ucast_packets" },
{ STATS_OFFSET32(total_multicast_packets_transmitted_hi),
8, false, "tx_mcast_packets" },
{ STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
8, false, "tx_bcast_packets" },
{ STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
8, true, "tx_mac_errors" },
{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
8, true, "tx_carrier_errors" },
/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
8, true, "tx_single_collisions" },
{ STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
8, true, "tx_multi_collisions" },
{ STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
8, true, "tx_deferred" },
{ STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
8, true, "tx_excess_collisions" },
{ STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
8, true, "tx_late_collisions" },
{ STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
8, true, "tx_total_collisions" },
{ STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
8, true, "tx_64_byte_packets" },
{ STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
8, true, "tx_65_to_127_byte_packets" },
{ STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
8, true, "tx_128_to_255_byte_packets" },
{ STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
8, true, "tx_256_to_511_byte_packets" },
/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
8, true, "tx_512_to_1023_byte_packets" },
{ STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
8, true, "tx_1024_to_1522_byte_packets" },
{ STATS_OFFSET32(etherstatspktsover1522octets_hi),
8, true, "tx_1523_to_9022_byte_packets" },
{ STATS_OFFSET32(pause_frames_sent_hi),
8, true, "tx_pause_frames" },
{ STATS_OFFSET32(total_tpa_aggregations_hi),
8, false, "tpa_aggregations" },
{ STATS_OFFSET32(total_tpa_aggregated_frames_hi),
8, false, "tpa_aggregated_frames"},
{ STATS_OFFSET32(total_tpa_bytes_hi),
8, false, "tpa_bytes"},
{ STATS_OFFSET32(recoverable_error),
4, false, "recoverable_errors" },
{ STATS_OFFSET32(unrecoverable_error),
4, false, "unrecoverable_errors" },
{ STATS_OFFSET32(driver_filtered_tx_pkt),
4, false, "driver_filtered_tx_pkt" },
{ STATS_OFFSET32(eee_tx_lpi),
4, true, "Tx LPI entry count"},
{ STATS_OFFSET32(ptp_skip_tx_ts),
4, false, "ptp_skipped_tx_tstamp" },
};
#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
static int bnx2x_get_port_type(struct bnx2x *bp)
{
int port_type;
u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
switch (bp->link_params.phy[phy_idx].media_type) {
case ETH_PHY_SFPP_10G_FIBER:
case ETH_PHY_SFP_1G_FIBER:
case ETH_PHY_XFP_FIBER:
case ETH_PHY_KR:
case ETH_PHY_CX4:
port_type = PORT_FIBRE;
break;
case ETH_PHY_DA_TWINAX:
port_type = PORT_DA;
break;
case ETH_PHY_BASE_T:
port_type = PORT_TP;
break;
case ETH_PHY_NOT_PRESENT:
port_type = PORT_NONE;
break;
case ETH_PHY_UNSPECIFIED:
default:
port_type = PORT_OTHER;
break;
}
return port_type;
}
static int bnx2x_get_vf_link_ksettings(struct net_device *dev,
struct ethtool_link_ksettings *cmd)
{
struct bnx2x *bp = netdev_priv(dev);
u32 supported, advertising;
ethtool_convert_link_mode_to_legacy_u32(&supported,
cmd->link_modes.supported);
ethtool_convert_link_mode_to_legacy_u32(&advertising,
cmd->link_modes.advertising);
if (bp->state == BNX2X_STATE_OPEN) {
if (test_bit(BNX2X_LINK_REPORT_FD,
&bp->vf_link_vars.link_report_flags))
cmd->base.duplex = DUPLEX_FULL;
else
cmd->base.duplex = DUPLEX_HALF;
cmd->base.speed = bp->vf_link_vars.line_speed;
} else {
cmd->base.duplex = DUPLEX_UNKNOWN;
cmd->base.speed = SPEED_UNKNOWN;
}
cmd->base.port = PORT_OTHER;
cmd->base.phy_address = 0;
cmd->base.autoneg = AUTONEG_DISABLE;
DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
" supported 0x%x advertising 0x%x speed %u\n"
" duplex %d port %d phy_address %d\n"
" autoneg %d\n",
cmd->base.cmd, supported, advertising,
cmd->base.speed,
cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
cmd->base.autoneg);
return 0;
}
static int bnx2x_get_link_ksettings(struct net_device *dev,
struct ethtool_link_ksettings *cmd)
{
struct bnx2x *bp = netdev_priv(dev);
int cfg_idx = bnx2x_get_link_cfg_idx(bp);
u32 media_type;
u32 supported, advertising, lp_advertising;
ethtool_convert_link_mode_to_legacy_u32(&lp_advertising,
cmd->link_modes.lp_advertising);
/* Dual Media boards present all available port types */
supported = bp->port.supported[cfg_idx] |
(bp->port.supported[cfg_idx ^ 1] &
(SUPPORTED_TP | SUPPORTED_FIBRE));
advertising = bp->port.advertising[cfg_idx];
media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
if (media_type == ETH_PHY_SFP_1G_FIBER) {
supported &= ~(SUPPORTED_10000baseT_Full);
advertising &= ~(ADVERTISED_10000baseT_Full);
}
if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
!(bp->flags & MF_FUNC_DIS)) {
cmd->base.duplex = bp->link_vars.duplex;
if (IS_MF(bp) && !BP_NOMCP(bp))
cmd->base.speed = bnx2x_get_mf_speed(bp);
else
cmd->base.speed = bp->link_vars.line_speed;
} else {
cmd->base.duplex = DUPLEX_UNKNOWN;
cmd->base.speed = SPEED_UNKNOWN;
}
cmd->base.port = bnx2x_get_port_type(bp);
cmd->base.phy_address = bp->mdio.prtad;
if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
cmd->base.autoneg = AUTONEG_ENABLE;
else
cmd->base.autoneg = AUTONEG_DISABLE;
/* Publish LP advertised speeds and FC */
if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
u32 status = bp->link_vars.link_status;
lp_advertising |= ADVERTISED_Autoneg;
if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
lp_advertising |= ADVERTISED_Pause;
if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
lp_advertising |= ADVERTISED_Asym_Pause;
if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
lp_advertising |= ADVERTISED_10baseT_Half;
if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
lp_advertising |= ADVERTISED_10baseT_Full;
if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
lp_advertising |= ADVERTISED_100baseT_Half;
if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
lp_advertising |= ADVERTISED_100baseT_Full;
if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
lp_advertising |= ADVERTISED_1000baseT_Half;
if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
if (media_type == ETH_PHY_KR) {
lp_advertising |=
ADVERTISED_1000baseKX_Full;
} else {
lp_advertising |=
ADVERTISED_1000baseT_Full;
}
}
if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
lp_advertising |= ADVERTISED_2500baseX_Full;
if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
if (media_type == ETH_PHY_KR) {
lp_advertising |=
ADVERTISED_10000baseKR_Full;
} else {
lp_advertising |=
ADVERTISED_10000baseT_Full;
}
}
if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
lp_advertising |= ADVERTISED_20000baseKR2_Full;
}
ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
supported);
ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
advertising);
ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
lp_advertising);
DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
" supported 0x%x advertising 0x%x speed %u\n"
" duplex %d port %d phy_address %d\n"
" autoneg %d\n",
cmd->base.cmd, supported, advertising,
cmd->base.speed,
cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
cmd->base.autoneg);
return 0;
}
static int bnx2x_set_link_ksettings(struct net_device *dev,
const struct ethtool_link_ksettings *cmd)
{
struct bnx2x *bp = netdev_priv(dev);
u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
u32 speed, phy_idx;
u32 supported;
u8 duplex = cmd->base.duplex;
ethtool_convert_link_mode_to_legacy_u32(&supported,
cmd->link_modes.supported);
ethtool_convert_link_mode_to_legacy_u32(&advertising,
cmd->link_modes.advertising);
if (IS_MF_SD(bp))
return 0;
DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
" supported 0x%x advertising 0x%x speed %u\n"
" duplex %d port %d phy_address %d\n"
" autoneg %d\n",
cmd->base.cmd, supported, advertising,
cmd->base.speed,
cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
cmd->base.autoneg);
speed = cmd->base.speed;
/* If received a request for an unknown duplex, assume full*/
if (duplex == DUPLEX_UNKNOWN)
duplex = DUPLEX_FULL;
if (IS_MF_SI(bp)) {
u32 part;
u32 line_speed = bp->link_vars.line_speed;
/* use 10G if no link detected */
if (!line_speed)
line_speed = 10000;
if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
DP(BNX2X_MSG_ETHTOOL,
"To set speed BC %X or higher is required, please upgrade BC\n",
REQ_BC_VER_4_SET_MF_BW);
return -EINVAL;
}
part = (speed * 100) / line_speed;
if (line_speed < speed || !part) {
DP(BNX2X_MSG_ETHTOOL,
"Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
return -EINVAL;
}
if (bp->state != BNX2X_STATE_OPEN)
/* store value for following "load" */
bp->pending_max = part;
else
bnx2x_update_max_mf_config(bp, part);
return 0;
}
cfg_idx = bnx2x_get_link_cfg_idx(bp);
old_multi_phy_config = bp->link_params.multi_phy_config;
if (cmd->base.port != bnx2x_get_port_type(bp)) {
switch (cmd->base.port) {
case PORT_TP:
if (!(bp->port.supported[0] & SUPPORTED_TP ||
bp->port.supported[1] & SUPPORTED_TP)) {
DP(BNX2X_MSG_ETHTOOL,
"Unsupported port type\n");
return -EINVAL;
}
bp->link_params.multi_phy_config &=
~PORT_HW_CFG_PHY_SELECTION_MASK;
if (bp->link_params.multi_phy_config &
PORT_HW_CFG_PHY_SWAPPED_ENABLED)
bp->link_params.multi_phy_config |=
PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
else
bp->link_params.multi_phy_config |=
PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
break;
case PORT_FIBRE:
case PORT_DA:
case PORT_NONE:
if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
bp->port.supported[1] & SUPPORTED_FIBRE)) {
DP(BNX2X_MSG_ETHTOOL,
"Unsupported port type\n");
return -EINVAL;
}
bp->link_params.multi_phy_config &=
~PORT_HW_CFG_PHY_SELECTION_MASK;
if (bp->link_params.multi_phy_config &
PORT_HW_CFG_PHY_SWAPPED_ENABLED)
bp->link_params.multi_phy_config |=
PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
else
bp->link_params.multi_phy_config |=
PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
break;
default:
DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
return -EINVAL;
}
}
/* Save new config in case command complete successfully */
new_multi_phy_config = bp->link_params.multi_phy_config;
/* Get the new cfg_idx */
cfg_idx = bnx2x_get_link_cfg_idx(bp);
/* Restore old config in case command failed */
bp->link_params.multi_phy_config = old_multi_phy_config;
DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
if (cmd->base.autoneg == AUTONEG_ENABLE) {
u32 an_supported_speed = bp->port.supported[cfg_idx];
if (bp->link_params.phy[EXT_PHY1].type ==
PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
an_supported_speed |= (SUPPORTED_100baseT_Half |
SUPPORTED_100baseT_Full);
if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
return -EINVAL;
}
/* advertise the requested speed and duplex if supported */
if (advertising & ~an_supported_speed) {
DP(BNX2X_MSG_ETHTOOL,
"Advertisement parameters are not supported\n");
return -EINVAL;
}
bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
bp->link_params.req_duplex[cfg_idx] = duplex;
bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
advertising);
if (advertising) {
bp->link_params.speed_cap_mask[cfg_idx] = 0;
if (advertising & ADVERTISED_10baseT_Half) {
bp->link_params.speed_cap_mask[cfg_idx] |=
PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
}
if (advertising & ADVERTISED_10baseT_Full)
bp->link_params.speed_cap_mask[cfg_idx] |=
PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
if (advertising & ADVERTISED_100baseT_Full)
bp->link_params.speed_cap_mask[cfg_idx] |=
PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
if (advertising & ADVERTISED_100baseT_Half) {
bp->link_params.speed_cap_mask[cfg_idx] |=
PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
}
if (advertising & ADVERTISED_1000baseT_Half) {
bp->link_params.speed_cap_mask[cfg_idx] |=
PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
}
if (advertising & (ADVERTISED_1000baseT_Full |
ADVERTISED_1000baseKX_Full))
bp->link_params.speed_cap_mask[cfg_idx] |=
PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
if (advertising & (ADVERTISED_10000baseT_Full |
ADVERTISED_10000baseKX4_Full |
ADVERTISED_10000baseKR_Full))
bp->link_params.speed_cap_mask[cfg_idx] |=
PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
if (advertising & ADVERTISED_20000baseKR2_Full)
bp->link_params.speed_cap_mask[cfg_idx] |=
PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
}
} else { /* forced speed */
/* advertise the requested speed and duplex if supported */
switch (speed) {
case SPEED_10:
if (duplex == DUPLEX_FULL) {
if (!(bp->port.supported[cfg_idx] &
SUPPORTED_10baseT_Full)) {
DP(BNX2X_MSG_ETHTOOL,
"10M full not supported\n");
return -EINVAL;
}
advertising = (ADVERTISED_10baseT_Full |
ADVERTISED_TP);
} else {
if (!(bp->port.supported[cfg_idx] &
SUPPORTED_10baseT_Half)) {
DP(BNX2X_MSG_ETHTOOL,
"10M half not supported\n");
return -EINVAL;
}
advertising = (ADVERTISED_10baseT_Half |
ADVERTISED_TP);
}
break;
case SPEED_100:
if (duplex == DUPLEX_FULL) {
if (!(bp->port.supported[cfg_idx] &
SUPPORTED_100baseT_Full)) {
DP(BNX2X_MSG_ETHTOOL,
"100M full not supported\n");
return -EINVAL;
}
advertising = (ADVERTISED_100baseT_Full |
ADVERTISED_TP);
} else {
if (!(bp->port.supported[cfg_idx] &
SUPPORTED_100baseT_Half)) {
DP(BNX2X_MSG_ETHTOOL,
"100M half not supported\n");
return -EINVAL;
}
advertising = (ADVERTISED_100baseT_Half |
ADVERTISED_TP);
}
break;
case SPEED_1000:
if (duplex != DUPLEX_FULL) {
DP(BNX2X_MSG_ETHTOOL,
"1G half not supported\n");
return -EINVAL;
}
if (bp->port.supported[cfg_idx] &
SUPPORTED_1000baseT_Full) {
advertising = (ADVERTISED_1000baseT_Full |
ADVERTISED_TP);
} else if (bp->port.supported[cfg_idx] &
SUPPORTED_1000baseKX_Full) {
advertising = ADVERTISED_1000baseKX_Full;
} else {
DP(BNX2X_MSG_ETHTOOL,
"1G full not supported\n");
return -EINVAL;
}
break;
case SPEED_2500:
if (duplex != DUPLEX_FULL) {
DP(BNX2X_MSG_ETHTOOL,
"2.5G half not supported\n");
return -EINVAL;
}
if (!(bp->port.supported[cfg_idx]
& SUPPORTED_2500baseX_Full)) {
DP(BNX2X_MSG_ETHTOOL,
"2.5G full not supported\n");
return -EINVAL;
}
advertising = (ADVERTISED_2500baseX_Full |
ADVERTISED_TP);
break;
case SPEED_10000:
if (duplex != DUPLEX_FULL) {
DP(BNX2X_MSG_ETHTOOL,
"10G half not supported\n");
return -EINVAL;
}
phy_idx = bnx2x_get_cur_phy_idx(bp);
if ((bp->port.supported[cfg_idx] &
SUPPORTED_10000baseT_Full) &&
(bp->link_params.phy[phy_idx].media_type !=
ETH_PHY_SFP_1G_FIBER)) {
advertising = (ADVERTISED_10000baseT_Full |
ADVERTISED_FIBRE);
} else if (bp->port.supported[cfg_idx] &
SUPPORTED_10000baseKR_Full) {
advertising = (ADVERTISED_10000baseKR_Full |
ADVERTISED_FIBRE);
} else {
DP(BNX2X_MSG_ETHTOOL,
"10G full not supported\n");
return -EINVAL;
}
break;
default:
DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
return -EINVAL;
}
bp->link_params.req_line_speed[cfg_idx] = speed;
bp->link_params.req_duplex[cfg_idx] = duplex;
bp->port.advertising[cfg_idx] = advertising;
}
DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
" req_duplex %d advertising 0x%x\n",
bp->link_params.req_line_speed[cfg_idx],
bp->link_params.req_duplex[cfg_idx],
bp->port.advertising[cfg_idx]);
/* Set new config */
bp->link_params.multi_phy_config = new_multi_phy_config;
if (netif_running(dev)) {
bnx2x_stats_handle(bp, STATS_EVENT_STOP);
bnx2x_force_link_reset(bp);
bnx2x_link_set(bp);
}
return 0;
}
#define DUMP_ALL_PRESETS 0x1FFF
#define DUMP_MAX_PRESETS 13
static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
{
if (CHIP_IS_E1(bp))
return dump_num_registers[0][preset-1];
else if (CHIP_IS_E1H(bp))
return dump_num_registers[1][preset-1];
else if (CHIP_IS_E2(bp))
return dump_num_registers[2][preset-1];
else if (CHIP_IS_E3A0(bp))
return dump_num_registers[3][preset-1];
else if (CHIP_IS_E3B0(bp))
return dump_num_registers[4][preset-1];
else
return 0;
}
static int __bnx2x_get_regs_len(struct bnx2x *bp)
{
u32 preset_idx;
int regdump_len = 0;
/* Calculate the total preset regs length */
for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
return regdump_len;
}
static int bnx2x_get_regs_len(struct net_device *dev)
{
struct bnx2x *bp = netdev_priv(dev);
int regdump_len = 0;
if (IS_VF(bp))
return 0;
regdump_len = __bnx2x_get_regs_len(bp);
regdump_len *= 4;
regdump_len += sizeof(struct dump_header);
return regdump_len;
}
#define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
#define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
#define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
#define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
#define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
#define IS_REG_IN_PRESET(presets, idx) \
((presets & (1 << (idx-1))) == (1 << (idx-1)))
/******* Paged registers info selectors ********/
static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
{
if (CHIP_IS_E2(bp))
return page_vals_e2;
else if (CHIP_IS_E3(bp))
return page_vals_e3;
else
return NULL;
}
static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
{
if (CHIP_IS_E2(bp))
return PAGE_MODE_VALUES_E2;
else if (CHIP_IS_E3(bp))
return PAGE_MODE_VALUES_E3;
else
return 0;
}
static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
{
if (CHIP_IS_E2(bp))
return page_write_regs_e2;
else if (CHIP_IS_E3(bp))
return page_write_regs_e3;
else
return NULL;
}
static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
{
if (CHIP_IS_E2(bp))
return PAGE_WRITE_REGS_E2;
else if (CHIP_IS_E3(bp))
return PAGE_WRITE_REGS_E3;
else
return 0;
}
static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
{
if (CHIP_IS_E2(bp))
return page_read_regs_e2;
else if (CHIP_IS_E3(bp))
return page_read_regs_e3;
else
return NULL;
}
static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
{
if (CHIP_IS_E2(bp))
return PAGE_READ_REGS_E2;
else if (CHIP_IS_E3(bp))
return PAGE_READ_REGS_E3;
else
return 0;
}
static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
const struct reg_addr *reg_info)
{
if (CHIP_IS_E1(bp))
return IS_E1_REG(reg_info->chips);
else if (CHIP_IS_E1H(bp))
return IS_E1H_REG(reg_info->chips);
else if (CHIP_IS_E2(bp))
return IS_E2_REG(reg_info->chips);
else if (CHIP_IS_E3A0(bp))
return IS_E3A0_REG(reg_info->chips);
else if (CHIP_IS_E3B0(bp))
return IS_E3B0_REG(reg_info->chips);
else
return false;
}
static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
const struct wreg_addr *wreg_info)
{
if (CHIP_IS_E1(bp))
return IS_E1_REG(wreg_info->chips);
else if (CHIP_IS_E1H(bp))
return IS_E1H_REG(wreg_info->chips);
else if (CHIP_IS_E2(bp))
return IS_E2_REG(wreg_info->chips);
else if (CHIP_IS_E3A0(bp))
return IS_E3A0_REG(wreg_info->chips);
else if (CHIP_IS_E3B0(bp))
return IS_E3B0_REG(wreg_info->chips);
else
return false;
}
/**
* bnx2x_read_pages_regs - read "paged" registers
*
* @bp: device handle
* @p: output buffer
* @preset: the preset value
*
* Reads "paged" memories: memories that may only be read by first writing to a
* specific address ("write address") and then reading from a specific address
* ("read address"). There may be more than one write address per "page" and
* more than one read address per write address.
*/
static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
{
u32 i, j, k, n;
/* addresses of the paged registers */
const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
/* number of paged registers */
int num_pages = __bnx2x_get_page_reg_num(bp);
/* write addresses */
const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
/* number of write addresses */
int write_num = __bnx2x_get_page_write_num(bp);
/* read addresses info */
const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
/* number of read addresses */
int read_num = __bnx2x_get_page_read_num(bp);
u32 addr, size;
for (i = 0; i < num_pages; i++) {
for (j = 0; j < write_num; j++) {
REG_WR(bp, write_addr[j], page_addr[i]);
for (k = 0; k < read_num; k++) {
if (IS_REG_IN_PRESET(read_addr[k].presets,
preset)) {
size = read_addr[k].size;
for (n = 0; n < size; n++) {
addr = read_addr[k].addr + n*4;
*p++ = REG_RD(bp, addr);
}
}
}
}
}
}
static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
{
u32 i, j, addr;
const struct wreg_addr *wreg_addr_p = NULL;
if (CHIP_IS_E1(bp))
wreg_addr_p = &wreg_addr_e1;
else if (CHIP_IS_E1H(bp))
wreg_addr_p = &wreg_addr_e1h;
else if (CHIP_IS_E2(bp))
wreg_addr_p = &wreg_addr_e2;
else if (CHIP_IS_E3A0(bp))
wreg_addr_p = &wreg_addr_e3;
else if (CHIP_IS_E3B0(bp))
wreg_addr_p = &wreg_addr_e3b0;
/* Read the idle_chk registers */
for (i = 0; i < IDLE_REGS_COUNT; i++) {
if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
for (j = 0; j < idle_reg_addrs[i].size; j++)
*p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
}
}
/* Read the regular registers */
for (i = 0; i < REGS_COUNT; i++) {
if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) &&
IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
for (j = 0; j < reg_addrs[i].size; j++)
*p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
}
}
/* Read the CAM registers */
if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
for (i = 0; i < wreg_addr_p->size; i++) {
*p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
/* In case of wreg_addr register, read additional
registers from read_regs array
*/
for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
addr = *(wreg_addr_p->read_regs);
*p++ = REG_RD(bp, addr + j*4);
}
}
}
/* Paged registers are supported in E2 & E3 only */
if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
/* Read "paged" registers */
bnx2x_read_pages_regs(bp, p, preset);
}
return 0;
}
static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
{
u32 preset_idx;
/* Read all registers, by reading all preset registers */
for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
/* Skip presets with IOR */
if ((preset_idx == 2) ||
(preset_idx == 5) ||
(preset_idx == 8) ||
(preset_idx == 11))
continue;
__bnx2x_get_preset_regs(bp, p, preset_idx);
p += __bnx2x_get_preset_regs_len(bp, preset_idx);
}
}
static void bnx2x_get_regs(struct net_device *dev,
struct ethtool_regs *regs, void *_p)
{
u32 *p = _p;
struct bnx2x *bp = netdev_priv(dev);
struct dump_header dump_hdr = {0};
regs->version = 2;
memset(p, 0, regs->len);
if (!netif_running(bp->dev))
return;
/* Disable parity attentions as long as following dump may
* cause false alarms by reading never written registers. We
* will re-enable parity attentions right after the dump.
*/
bnx2x_disable_blocks_parity(bp);
dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
dump_hdr.preset = DUMP_ALL_PRESETS;
dump_hdr.version = BNX2X_DUMP_VERSION;
/* dump_meta_data presents OR of CHIP and PATH. */
if (CHIP_IS_E1(bp)) {
dump_hdr.dump_meta_data = DUMP_CHIP_E1;
} else if (CHIP_IS_E1H(bp)) {
dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
} else if (CHIP_IS_E2(bp)) {
dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
} else if (CHIP_IS_E3A0(bp)) {
dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
} else if (CHIP_IS_E3B0(bp)) {
dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
(BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);