8051-c.ini

# 8051-c.ini
#
# ARCH = < 8051 | 80C517 | 80C751 >
#	8051 means standard architecture
#	80C517 means has 32-Bit ALU
#	80C751 is a chip whose maximum program size < 2048. Therefore some instructions
#	are not implimented.
# MAKE = <string>
#	Name of manufacturer of this chip.
# INTRAM = <hex_value>
#	Defines the upper limit of on-chip internal RAM which may be accessed indirectly.
#	Possible values are 40 (64bytes) ,80 (128bytes) ,C0 (192bytes) or 100 (256bytes).
# XRAM = <start address-end address>
#	How much on-chip, external data memory is available?
#	If XRAM is not defined, then chip's entire data memory will be located
#	in external memory.
# OFFRAM = <start address-end address>
#	Range of off-chip external data that can be added.
#	If OFFRAM is not defined, then external data is not available
#	for this chip. Therefore this chip's entire data memory cannot be expanded
#	from the value of XRAM.
# ROM = <start address-end address>
#	How much program memory is available on-board the chip?
#	If ROM is not defined, then chip's entire program memory will be located
#	in external memory.
# OFFROM = <start address-end address>
#	The range of addressable program memory.
#	Range of addressable data memory.
#	If OFFROM is not defined, then external prog memory is not available
#	for this chip. Therefore this chip's prog memory cannot be expanded
#	from the ranges defined by ROM.
# BANKROM = <start address-end address>
#	For chips that have supported banking ability, this attribute defines the
#	range of ROM addresses that are available for banking. This range may overlap the
#	range given by ROM=, in which case for huge model, the ROM range will be limited
#	to those addresses that do not overlap, i.e. BANKROM takes precedence over ROM.
#	This attribute is not used for standard model.
# BANKADR = <start address-end address>
#	The range where the banked memory can be found. This is defined only 
#	for those chips who support banked memory.
# BANKTYPE = < A | C | E | F | G | H | N | T | U | V | Z >
#	This criteria describes the method used when performing a bank switch.
#	Note that N is a special case that is reserved.
# INSTR = <set>
#	Describes which instruction set the chip uses. Any deviations from
#	the standard insruction set will be noted here. The standard
#	instruction set is called MCS-51.
# WATCHDOG = <string>
#	An assembler code sequence that will reset the watchdog, for use in startup
#	code.
# BANKSEL= <address>
#	Defines the address of the bank select register



[STC15W401AS]
MAKE = STC
INTRAM = 100
#512 ram
XRAM = 0-1FF
OFFRAM = 0-FFFF
#1k Rom
ROM=0-3FF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051 

[STC15W402AS]
MAKE = STC
INTRAM = 100
#512 ram
XRAM = 0-1FF
OFFRAM = 0-FFFF
#2k Rom
ROM=0-7FF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051 

[STC15W404AS]
MAKE = STC
INTRAM = 100
#512 ram
XRAM = 0-1FF
OFFRAM = 0-FFFF
#4k Rom
ROM=0-FFE
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051 

[STC15W408AS]
MAKE = STC
INTRAM = 100
#512 ram
XRAM = 0-1FF
OFFRAM = 0-FFFF
#8k Rom
ROM=0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051 

[STC8A8K64S4A12]
MAKE = STC
#
INTRAM = 100
#8K ram
XRAM = 0-1FFF
OFFRAM = 0-1FFF
#64k Rom
ROM=0-FDF0
#ROM = 0-FFFF
OFFROM = 0-FDFF
#BANKROM = 8000-FFFFF
#BANKADR = 8000-FFFF
#BANKTYPE = N
INSTR = MCS-51
ARCH = 8051 
#WATCHDOG = "mov 0xFE,a"

[STC8A8K60S4A12]
MAKE = STC
#
INTRAM = 100
#8K ram
XRAM = 0-1FFF
OFFRAM = 0-1FFF
#60k Rom
ROM=0-EFF0
#ROM = 0-FFFF
OFFROM = 0-EFFF
#BANKROM = 8000-FFFFF
#BANKADR = 8000-FFFF
#BANKTYPE = N
INSTR = MCS-51
ARCH = 8051 

[STC8A8K32S4A12]
MAKE = STC
#
INTRAM = 100
#8K ram
XRAM = 0-1FFF
OFFRAM = 0-1FFF
#32k Rom
ROM=0-7FF0
#ROM = 0-FFFF
OFFROM = 0-7FFF
#BANKROM = 8000-FFFFF
#BANKADR = 8000-FFFF
#BANKTYPE = N
INSTR = MCS-51
ARCH = 8051 

[STC8A8K16S4A12]
MAKE = STC
#
INTRAM = 100
#8K ram
XRAM = 0-1FFF
OFFRAM = 0-1FFF
#16k Rom
ROM=0-3FF0
#ROM = 0-FFFF
OFFROM = 0-3FFF
#BANKROM = 8000-FFFFF
#BANKADR = 8000-FFFF
#BANKTYPE = N
INSTR = MCS-51
ARCH = 8051 

[STC12XX5608AD]
MAKE = STC
INTRAM = F0
XRAM = 0-01FF
OFFRAM = 0-01FF
#8k
ROM = 0-1FF8		
OFFROM = 0-FFFF
#BANKROM = 8000-FFFFF
#BANKADR = 8000-FFFF
#BANKTYPE = N
INSTR = MCS-51
ARCH = 8051 
[STC12XX5624AD]
MAKE = STC
INTRAM = F0
XRAM = 0-01FF
OFFRAM = 0-01FF
#24k
ROM = 0-5FF8		
OFFROM = 0-FFFF
#BANKROM = 8000-FFFFF
#BANKADR = 8000-FFFF
#BANKTYPE = N
INSTR = MCS-51
ARCH = 8051 
[STC8F2K64S4]
MAKE = STC
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 0-1FFF
ROM = 0-FDFF
OFFROM = 0-FDFF
BANKROM = FE00-FFFF
BANKADR = FE00-FFFF
BANKTYPE = C
INSTR = MCS-51
ARCH = 80C751
[8051]
MAKE = GENERIC
INTRAM = 100
XRAM = 0-FFFF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
#BANKROM = 8000-FFFFF
BANKADR = 8000-FFFF
BANKTYPE = N
INSTR = MCS-51
ARCH = 8051

[8031AH]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8032AH]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8044]
MAKE = INTEL
INTRAM = C0
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8051AH]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8051AHP]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-0FFF
ROM = 0-0FFF
OFFROM = 0-0FFF
INSTR = MCS-51
ARCH = 8051
# protected version of 8051AH: prog verify disabled, limited ext access

[8052AH]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C151SA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has page mode

[80C151SB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has page mode

[80C152]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C152JA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C152JB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C152JC]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C152JD]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C31BH]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C32]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C51]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C51BH]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C51BHP]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-0FFF
ROM = 0-0FFF
OFFROM = 0-0FFF
INSTR = MCS-51
ARCH = 8051
# protected version of 80C51BH: prog verify disabled, limited extern access

[80C51FA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C51GB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C51RA]
MAKE = INTEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C517]
MAKE = GENERIC
INTRAM = 100
XRAM = 0-FFFF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 80C517

[80C52]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C537]
MAKE = GENERIC
INTRAM = 100
XRAM = 0-FFFF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 80C517

[80C54]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C58]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[80C751]
MAKE = GENERIC
INTRAM = 100
ROM = 0-7FF
INSTR = reduced MCS-51
ARCH = 80C751

[8344]
MAKE = INTEL
INTRAM = C0
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C151SA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C151SB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C152]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C152JA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C152JB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C152JC]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C152JD]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C51FA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C51FB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C51FC]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C51KB]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C51RA]
MAKE = INTEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C51RB]
MAKE = INTEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[83C51RC]
MAKE = INTEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8744]
MAKE = INTEL
INTRAM = C0
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8751BH]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8751H]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[8751H8]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# 8Mhz version of 8751H

[8752BH]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C151SA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C151SB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51]
MAKE = INTEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51FA]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51FB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51FC]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51GB]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51RA]
MAKE = INTEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51RB]
MAKE = INTEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C51RC]
MAKE = INTEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C52]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C54]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[87C58]
MAKE = INTEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[ADUC812]
MAKE = ANALOG
INTRAM = 100
XRAM = 0-9F
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has both data SRAM and data flash/EE on chip, this chip has 24-Bit addressing for data (we will support up to 16-Bit)
# data Flash/EE addressed between 0-9F can be paged. Under SFR control. 

[ADUC812S]
MAKE = ANALOG
INTRAM = 100
XRAM = 0-9F
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# has both data RAM and data flash/EE on chip
# data Flash/EE addressed between 0-9F can be paged. Under SFR control. 

[ADUC814]
MAKE = ANALOG
INTRAM = 100
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# has 640 bytes of EEPROM data memory

[ADUC816]
MAKE = ANALOG
INTRAM = 80
XRAM = 0-9F
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has both data RAM and data flash/EE on chip, this chip has 24-Bit addressing for data (we will only support 16-Bits)
# data Flash/EE addressed between 0-9F can be paged. Under SFR control. 

[ADUC824]
MAKE = ANALOG
INTRAM = 100
XRAM = 0-9F
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has both data RAM and data flash/EE on chip, this chip has 24-Bit addressing for data (we will only support 16-Bits)
# data Flash/EE addressed between 0-9F can be paged. Under SFR control. 

[ADUC831]
MAKE = ANALOG
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-F7FF
INSTR = MCS-51
ARCH = 8051
# has 4k of EEPROM data memory
# can access up to 16MB of external data memory
# has XRAM at 0-7FF, but is disabled by default, enabled via CFG831 sfr.

[ADUC832]
MAKE = ANALOG
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-F7FF
INSTR = MCS-51
ARCH = 8051
# has 4k of EEPROM data memory
# can access up to 16MB of external data memory
# has XRAM at 0-7FF, but is disabled by default, enabled via CFG832 sfr.

[ADUC834]
MAKE = ANALOG
INTRAM = 100
ROM = 0-F7FF
OFFRAM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 4k of EEPROM data memory
# can access up to 16MB of external data memory
# has XRAM at 0-7FF, but is disabled by default, enabled via CFG834 sfr.

[ADUC836]
MAKE = ANALOG
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 0-FFFF
ROM = 0-F7FF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR
# WARNING - this chip does not support rollover execution between
#           on-chip and off-chip program memory! IE use one or the
#           other - not both.
# can access up to 16MB of external data memory

[ADUC841]
MAKE = ANALOG
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 0-FFFF
ROM = 0-F7FF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR
# WARNING - this chip does not support rollover execution between
#           on-chip and off-chip program memory! IE use one or the
#           other - not both.
# can access up to 16MB of external data memory

[ADUC842]
MAKE = ANALOG
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 0-FFFF
ROM = 0-F7FF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR
# WARNING - this chip does not support rollover execution between
#           on-chip and off-chip program memory! IE use one or the
#           other - not both.
# can access up to 16MB of external data memory

[ADUC843]
MAKE = ANALOG
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 0-FFFF
ROM = 0-F7FF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR
# WARNING - this chip does not support rollover execution between
#           on-chip and off-chip program memory! IE use one or the
#           other - not both.
# can access up to 16MB of external data memory

[AM80C51]
MAKE = AMD
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AM80C52]
MAKE = AMD
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AM80C521]
MAKE = AMD
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AN2121S]
MAKE = CYPRESS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AN2122S]
MAKE = CYPRESS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AN2122T]
MAKE = CYPRESS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AN2125S]
MAKE = CYPRESS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AN2126S]
MAKE = CYPRESS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AN2126T]
MAKE = CYPRESS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AN2131Q]
MAKE = CYPRESS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Program is stored in RAM

[AN2131S]
MAKE = CYPRESS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Program is stored in RAM

[AN2135S]
MAKE = CYPRESS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Program is stored in RAM

[AN2136S]
MAKE = CYPRESS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Program is stored in RAM

[AT48801]
MAKE = ATMEL
INTRAM = 100
ROM = 0-1FFF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT80C5112]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT80C51SND1C]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM is software resizable

[AT80F52]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT83C5103]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
ROM = 0-2FFF
INSTR = MCS-51
ARCH = 8051

[AT83C5111]
MAKE = ATMEL
INTRAM = 100
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT83C5112]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT83C5123]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-1FF
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[AT83C5132]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# on chip ERAM can be resized/deselected via SFR controls

[AT83C51SND1A]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 800-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 4K of Boot memory
# data is only preliminary 

[AT83EB5123]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-1FF
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# also has 256 bytes of EEPROM

[AT83SND1C]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM is software resizable

[AT83SND2C]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM is software resizable

[AT87C5103]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
ROM = 0-2FFF
INSTR = MCS-51
ARCH = 8051

[AT87C5111]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT87C5112]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT87F51RC]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT87F51]
MAKE = ATMEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT87F52]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT87F55WD]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-4FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT87LV51]
MAKE = ATMEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT87LV52]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT87LV55]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-4FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT89C1051]
MAKE = ATMEL
INTRAM = 40
ROM = 0-3FF
INSTR = restrictions on memory access instructions to MCS-51 set
ARCH = 80C751

[AT89C1051U]
MAKE = ATMEL
INTRAM = 40
ROM = 0-3FF
INSTR = restrictions on memory access instructions to MCS-51 set
ARCH = 80C751

[AT89C2051]
MAKE = ATMEL
INTRAM = 80
ROM = 0-7FF
INSTR = restrictions on memory access instructions to MCS-51 set
ARCH = 80C751

[AT89C4051]
MAKE = ATMEL
INTRAM = 80
ROM = 0-0FFF
INSTR = MCS-51
ARCH = 8051

[AT89C5131]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 400-FFFF
ROM = 0-7FFF
OFFROM = 8000-FFFF
INSTR = MCS-51
ARCH = 8051
# has section of boot flash F400h-FFFF if enabled via AUXR SFR
# has EEPROM from 0-3FFh, can be accessed with MOVX if EEE bit is set.
# note EEE should be clear in order to access ERAM with MOVX.

[AT89C5132]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# on chip ERAM can be resized/deselected via SFR controls
# this AT89C part also has 4K of boot flash from F000-FFFF

[AT89C51ED2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 300-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# The XRAM is configurable in software. Sizes are 100h,200h,300h(default),400h,700h
# OFFRAM must begin where XRAM ends
# Also has 2048 bytes of EEPROM

[AT89C51ID2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 300-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 2048 bytes EEPROM
# The XRAM is configurable in software. Sizes are 0,100h,200h,300h(default),400h,700h
# OFFRAM must begin where XRAM ends

[AT89C51RB2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-3FFF
OFFROM = 8000-FFFF
INSTR = MCS-51
ARCH = 8051
# The XRAM is configurable in software. Sizes are 0,100h(default),200h,300h,400h
# OFFRAM must begin where XRAM ends

[AT89C51RC2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-7FFF
OFFROM = 8000-FFFF
INSTR = MCS-51
ARCH = 8051
# The XRAM is configurable in software. Sizes are 0,100h(default),200h,300h,400h
# OFFRAM must begin where XRAM ends

[AT89C51RC]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT89C51RD2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 300-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# The XRAM is configurable in software. Sizes are 100h,200h,300h(default),400h,700h
# OFFRAM must begin where XRAM ends

[AT89C51SND1A]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 800-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 4K of Boot memory
# data is only preliminary 

[AT89C51SND1C]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM is software resizable
# Has a seperate 4K of boot flash at F000-FFFF

[AT89C51SND2C]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-7FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM is software resizable
# Has a seperate 4K of boot flash at F000-FFFF

[AT89C51]
MAKE = ATMEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT89C52]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT89C55]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-4FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT89C55WD]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-4FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT89LS51]
MAKE = ATMEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT89LS52]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT89LS53]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-2FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# specific instructions (codes) are used for serial programming

[AT89LS8252]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# specific instructions (codes) are used for serial programming, also has 2k of data EEPROM

[AT89LV51RC]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT89LV51]
MAKE = ATMEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT89LV52]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT89LV55WD]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-4FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT89LV55]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-4FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT89S4D12]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FFFF
ROM = 0-0FFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer, no external memory access, specific instructions are used for serial programming, on-chip external RAM exists up to 2FFFF!(128k)

[AT89S51]
MAKE = ATMEL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[AT89S52]
MAKE = ATMEL
INTRAM = 100
ROM = 0-1FFF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# specific instructions are used for serial programming

[AT89S53]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-2FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# specific instructions are used for serial programming

[AT89S8252]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# specific instructions are used for serial programming, also has 2k data EEPROM

[C501_1E]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C501_1R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C501_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C504_2E]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C504_2R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C504_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C505_2R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C505A_2R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C505A_4E]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C505A_4R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C505A_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C505C_2R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C505CA_2R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C505CA_4E]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C505CA_4R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C505CA_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C505C_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C505L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C505_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C508_4E]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C508_4R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C509_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 80C517
# has XRAM positioned at F400-FFFF, this is enabled by XMAP bit.
# has boot ROM from 0-1FF.
# has 4 diff modes, each has diff memory ranges.

[C511A_R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C511_R]
MAKE = INFINEON
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-9FF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C513_1R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C513A_2R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C513A_H]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-2FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C513A_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C513AO_2E]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C513AO_2R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C513AO_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C513A_R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-2FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C515_1R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C515A_4R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C515A_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C515C_8E]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# external memory may be used as an alternative to on chip memory.
# 2K XRAM (F800-FFFF) and 256b CAN-registers (F700-F7FF) are on-chip,
# but disabled by default.

[C515C_8R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# external memory may be used as an alternative to on chip memory.
# 2K XRAM (F800-FFFF) and 256b CAN-registers (F700-F7FF) are on-chip,
# but disabled by default.

[C515C_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# 2K XRAM (F800-FFFF) and 256b CAN-registers (F700-F7FF) are on-chip,
# but disabled by default.

[C515_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C517A_4R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 80C517
# has XRAM positioned at F800-FFFF, this is enabled by XMAP bit.

[C517A_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 80C517
# has XRAM positioned at F800-FFFF, this is enabled by XMAP bit.

[C540U]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C540U_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C541U]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C541U_1E]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C541U_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C8051F000]
MAKE = SILABS
INTRAM = 100
ROM = 0-7DFD,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F001]
MAKE = SILABS
INTRAM = 100
ROM = 0-7DFD,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F002]
MAKE = SILABS
INTRAM = 100
ROM = 0-7DFD,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F005]
MAKE = SILABS
INTRAM = 100
XRAM = 0-7FF
ROM = 0-7DFD,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F006]
MAKE = SILABS
INTRAM = 100
XRAM = 0-7FF
ROM = 0-7DFD,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F007]
MAKE = SILABS
INTRAM = 100
XRAM = 0-7FF
ROM = 0-7DFD,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F010]
MAKE = SILABS
INTRAM = 100
ROM = 0-7DFD,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F011]
MAKE = SILABS
INTRAM = 100
ROM = 0-7DFD,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F012]
MAKE = SILABS
INTRAM = 100
ROM = 0-7DFD,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F015]
MAKE = SILABS
INTRAM = 100
XRAM = 0-7FF
ROM = 0-7DFD,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F016]
MAKE = SILABS
INTRAM = 100
XRAM = 0-7FF
ROM = 0-7DFD,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F017]
MAKE = SILABS
INTRAM = 100
XRAM = 0-7FF
ROM = 0-7DFD,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F018]
MAKE = SILABS
INTRAM = 100
XRAM = 0-03FF
ROM = 0-3DFd,8000-807F
INSTR = CIP-51
ARCH = 8051
# The XRAM window is repeated accross entire memory range
# CIP-51 is fully compatible with MCS-51

[C8051F019]
MAKE = SILABS
INTRAM = 100
XRAM = 0-03FF
ROM = 0-3DFd,8000-807F
INSTR = CIP-51
ARCH = 8051
# The XRAM window is repeated accross entire memory range
# this device has PORTS 0-3, but only 0 & 1 are pinned out
# CIP-51 is fully compatible with MCS-51

[C8051F020]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFd
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F021]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFd
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F022]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFd
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F023]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFd
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F040]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# CIP-51 is fully compatible with MCS-51

[C8051F041]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51

[C8051F042]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# CIP-51 is fully compatible with MCS-51

[C8051F043]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51

[C8051F044]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51

[C8051F045]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51

[C8051F046]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-7FFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51

[C8051F047]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-7FFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51

[C8051F060]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-FBFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51


[C8051F061]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-FBFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51


[C8051F062]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-FBFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51


[C8051F063]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-FBFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51

[C8051F064]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-FBFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51

[C8051F065]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-FBFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51

[C8051F066]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-FBFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51

[C8051F067]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-FBFD
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51


[C8051F120]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKROM=8000-1FBFD
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
BANKSEL=B1
# SFR space can be banked, up to 256 banks.
# PAGE0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for PAGE0.
# Note that in PAGE3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F121]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKROM = 8000-1FBFD
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be banked, up to 256 banks.
# PAGE0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for PAGE0.
# Note that in PAGE3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F122]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKROM = 8000-1FBFD
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be banked, up to 256 banks.
# PAGE0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for PAGE0.
# Note that in PAGE3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F123]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKROM = 8000-1FBFD
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be banked, up to 256 banks.
# PAGE0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for PAGE0.
# Note that in PAGE3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F124]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKROM = 8000-1FBFD
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be banked, up to 256 banks.
# PAGE0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for PAGE0.
# Note that in PAGE3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F125]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKROM = 8000-1FBFD
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be banked, up to 256 banks.
# PAGE0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for PAGE0.
# Note that in PAGE3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F126]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKROM = 8000-1FBFD
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be banked, up to 256 banks.
# PAGE0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for PAGE0.
# Note that in PAGE3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F127]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKROM = 8000-1FBFD
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be banked, up to 256 banks.
# PAGE0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for PAGE0.
# Note that in PAGE3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F130]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKROM = 8000-1FBFD
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be banked, up to 256 banks.
# PAGE0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for PAGE0.
# Note that in PAGE3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F131]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKROM = 8000-1FBFD
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be banked, up to 256 banks.
# PAGE0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for PAGE0.
# Note that in PAGE3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F132]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFD
INSTR = CIP-51
ARCH = 8051
# SFR space can be banked, up to 256 banks.
# Also scratchpad memory at 20000-200FF.

[C8051F133]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFD
INSTR = CIP-51
ARCH = 8051
# SFR space can be banked up to 256 banks.
# Also scratchpad memory at 20000-200FF.

[C8051F206]
MAKE = SILABS
INTRAM = 100
XRAM = 0-03FF
ROM = 0-1DFD,2000-207F
INSTR = CIP-51
ARCH = 8051
# 1k external data memory is repeated throughout 64k memory, CIP-51 is fully compatible with MCS-51

[C8051F220]
MAKE = SILABS
INTRAM = 100
ROM = 0-1DFD,2000-207F
INSTR = CIP-51
ARCH = 8051
# 1k external data memory is repeated throughout 64k memory, CIP-51 is fully compatible with MCS-51

[C8051F221]
MAKE = SILABS
INTRAM = 100
ROM = 0-1DFD,2000-207F
INSTR = CIP-51
ARCH = 8051
# 1k external data memory is repeated throughout 64k memory, CIP-51 is fully compatible with MCS-51

[C8051F226]
MAKE = SILABS
INTRAM = 100
XRAM = 0-03FF
ROM = 0-1DFD,2000-207F
INSTR = CIP-51
ARCH = 8051
# 1k external data memory is repeated throughout 64k memory, CIP-51 is fully compatible with MCS-51

[C8051F230]
MAKE = SILABS
INTRAM = 100
ROM = 0-1DFD,2000-207F
INSTR = CIP-51
ARCH = 8051
# 1k external data memory is repeated throughout 64k memory, CIP-51 is fully compatible with MCS-51

[C8051F231]
MAKE = SILABS
INTRAM = 100
ROM = 0-1DFD,2000-207F
INSTR = CIP-51
ARCH = 8051
# 1k external data memory is repeated throughout 64k memory, CIP-51 is fully compatible with MCS-51

[C8051F236]
MAKE = SILABS
INTRAM = 100
XRAM = 0-03FF
ROM = 0-1DFD,2000-207F
INSTR = CIP-51
ARCH = 8051
# 1k external data memory is repeated throughout 64k memory, CIP-51 is fully compatible with MCS-51

[C8051F300]
MAKE = SILABS
INTRAM = 100
ROM = 0-1DFD
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F301]
MAKE = SILABS
INTRAM = 100
ROM = 0-1DFD
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F302]
MAKE = SILABS
INTRAM = 100
ROM = 0-1DFD
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F303]
MAKE = SILABS
INTRAM = 100
ROM = 0-1DFD
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F304]
MAKE = SILABS
INTRAM = 100
ROM = 0-0FFD
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F305]
MAKE = SILABS
INTRAM = 100
ROM = 0-07FD
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F310]
MAKE = SILABS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-3DFE
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51
# Not all of Port 3 is pinned out

[C8051F311]
MAKE = SILABS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-3DFE
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51
# Not all of Port 3 is pinned out

[C8051F312]
MAKE = SILABS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-1FFE
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51
# Not all of Port 3 is pinned out

[C8051F313]
MAKE = SILABS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-1FFE
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51
# Not all of Port 3 is pinned out

[C8051F314]
MAKE = SILABS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-1FFE
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51
# Not all of Port 3 is pinned out

[C8051F315]
MAKE = SILABS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-1FFE
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51
# Not all of Port 3 is pinned out

[C8051F316]
MAKE = SILABS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-3DFE
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51
# Not all of Port 3 is pinned out

[C8051F317]
MAKE = SILABS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-3DFE
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51
# Not all of Port 3 is pinned out

[C8051F320]
MAKE = SILABS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-3DFE
INSTR = CIP-51
ARCH = 8051
WATCHDOG = "mov 0xFE,a"
# has USB FIFOs from 400-7FF

[C8051F321]
MAKE = SILABS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-3DFE
INSTR = CIP-51
ARCH = 8051
WATCHDOG = "mov 0xFE,a"
# has USB FIFOs from 400-7FF

[C8051F326]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-3DFE
INSTR = CIP-51
ARCH = 8051

[C8051F327]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-3DFE
INSTR = CIP-51
ARCH = 8051

[C8051F330]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-1DFE
INSTR = CIP-51
ARCH = 8051

[C8051F330D]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-1DFE
INSTR = CIP-51
ARCH = 8051

[C8051F331]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-1DFE
INSTR = CIP-51
ARCH = 8051

[C8051F332]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-FFE
INSTR = CIP-51
ARCH = 8051

[C8051F333]
MAKE = SILABS
INTRAM = 100
XRAM =  0-1FF
ROM = 0-0FFE
INSTR = CIP-51
ARCH = 8051


[C8051F334]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-7FE
INSTR = CIP-51
ARCH = 8051

[C8051F335]
MAKE = SILABS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-7FE
INSTR = CIP-51
ARCH = 8051

[C8051F336]
MAKE = SILABS
INTRAM = 100
XRAM =  0-1FF
ROM = 0-3DFE
INSTR = CIP-51
ARCH = 8051

[C8051F337]
MAKE = SILABS
INTRAM = 100
XRAM =  0-1FF
ROM = 0-3DFE
INSTR = CIP-51
ARCH = 8051

[C8051F338]
MAKE = SILABS
INTRAM = 100
XRAM =  0-1FF
ROM = 0-3DFE
INSTR = CIP-51
ARCH = 8051

[C8051F339]
MAKE = SILABS
INTRAM = 100
XRAM =  0-1FF
ROM = 0-3DFE
INSTR = CIP-51
ARCH = 8051

[C8051F340]
MAKE = SILABS
INTRAM = 100
XRAM = 0-03FF
XRAM = 800-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FBFE
INSTR = CIP-51
ARCH = 8051
# XDATA from 400-7FF is used by USB
# MOVX to USB space only possible if SFRs enable this access

[C8051F341]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-7FFE
INSTR = CIP-51
ARCH = 8051
# XDATA from 400-7FF is used by USB
# MOVX to USB space only possible if SFRs enable this access

[C8051F342]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-FBFE
INSTR = CIP-51
ARCH = 8051
# XDATA from 400-7FF is used by USB
# MOVX to USB space only possible if SFRs enable this access

[C8051F343]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-7FFE
INSTR = CIP-51
ARCH = 8051
# XDATA from 400-7FF is used by USB
# MOVX to USB space only possible if SFRs enable this access

[C8051F344]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FBFE
INSTR = CIP-51
ARCH = 8051
# XDATA from 400-7FF is used by USB
# MOVX to USB space only possible if SFRs enable this access

[C8051F345]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-7FFE
INSTR = CIP-51
ARCH = 8051
# XDATA from 400-7FF is used by USB
# MOVX to USB space only possible if SFRs enable this access

[C8051F346]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-FBFE
INSTR = CIP-51
ARCH = 8051
# XDATA from 400-7FF is used by USB
# MOVX to USB space only possible if SFRs enable this access

[C8051F347]
MAKE = SILABS
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-7FFE
INSTR = CIP-51
ARCH = 8051
# XDATA from 400-7FF is used by USB
# MOVX to USB space only possible if SFRs enable this access

[C8051F350]
MAKE = SILABS
INTRAM = 100
XRAM =  0-1FF
ROM = 0-1DFE
INSTR = CIP-51
ARCH = 8051

[C8051F351]
MAKE = SILABS
INTRAM = 100
XRAM =  0-1FF
ROM = 0-1DFE
INSTR = CIP-51
ARCH = 8051

[C8051F352]
MAKE = SILABS
INTRAM = 100
XRAM =  0-1FF
ROM = 0-1DFE
INSTR = CIP-51
ARCH = 8051

[C8051F353]
MAKE = SILABS
INTRAM = 100
XRAM =  0-1FF
ROM = 0-1DFE
INSTR = CIP-51
ARCH = 8051

[C8051F360]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-7BFE
INSTR = CIP-51
ARCH = 8051


[C8051F361]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-7BFE
INSTR = CIP-51
ARCH = 8051

[C8051F362]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-7BFE
INSTR = CIP-51
ARCH = 8051

[C8051F363]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-7BFE
INSTR = CIP-51
ARCH = 8051

[C8051F364]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-7BFE
INSTR = CIP-51
ARCH = 8051

[C8051F365]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-7BFE
INSTR = CIP-51
ARCH = 8051

[C8051F366]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-7BFE
INSTR = CIP-51
ARCH = 8051

[C8051F367]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-7BFE
INSTR = CIP-51
ARCH = 8051

[C8051F368]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-3FFE
INSTR = CIP-51
ARCH = 8051

[C8051F369]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-3FFE
INSTR = CIP-51
ARCH = 8051

[C8051F410]
MAKE = SILABS
INTRAM = 100
XRAM =  0-7FF
ROM = 0-7DFE
INSTR = CIP-51
ARCH = 8051

[C8051F411]
MAKE = SILABS
INTRAM = 100
XRAM =  0-7FF
ROM = 0-7DFE
INSTR = CIP-51
ARCH = 8051


[C8051F412]
MAKE = SILABS
INTRAM = 100
XRAM =  0-7FF
ROM = 0-3FFE
INSTR = CIP-51
ARCH = 8051


[C8051F413]
MAKE = SILABS
INTRAM = 100
XRAM =  0-7FF
ROM = 0-3FFE
INSTR = CIP-51
ARCH = 8051

[C8051F520]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-1DFE
INSTR = CIP-51
ARCH = 8051


[C8051F521]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-1DFE
INSTR = CIP-51
ARCH = 8051

[C8051F523]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-0FFE
INSTR = CIP-51
ARCH = 8051

[C8051F524]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-0FFE
INSTR = CIP-51
ARCH = 8051


[C8051F526]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-7FE
INSTR = CIP-51
ARCH = 8051

[C8051F527]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-7FE
INSTR = CIP-51
ARCH = 8051



[C8051F530]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-1DFE
INSTR = CIP-51
ARCH = 8051


[C8051F531]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-1DFE
INSTR = CIP-51
ARCH = 8051


[C8051F533]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-0FFE
INSTR = CIP-51
ARCH = 8051

[C8051F534]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-0FFE
INSTR = CIP-51
ARCH = 8051

[C8051F536]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-7FE
INSTR = CIP-51
ARCH = 8051

[C8051F537]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-7FE
INSTR = CIP-51
ARCH = 8051

[C8051F920]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0FFF
OFFRAM = 1000-1FFF
ROM = 0-7FFE
INSTR = CIP-51
ARCH = 8051
# Also has BANK F for banked SFRs
# 0-3FF (progspace) accesses scratchpad flash when SFLE is 1

[C8051F921]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0FFF
ROM = 0-7FFE
INSTR = CIP-51
ARCH = 8051
# Also has BANK F for banked SFRs
# 0-3FF (progspace) accesses scratchpad flash when SFLE is 1

[C8051F930]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0FFF
OFFRAM = 1000-1FFF
ROM = 0-FBFE
INSTR = CIP-51
ARCH = 8051
# Also has BANK F for banked SFRs
# 0-3FF (progspace) accesses scratchpad flash when SFLE is 1

[C8051F931]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0FFF
ROM = 0-FBFE
INSTR = CIP-51
ARCH = 8051
# Also has BANK F for banked SFRs
# 0-3FF (progspace) accesses scratchpad flash when SFLE is 1

[C8051T600]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-1DFF
INSTR = CIP-51
ARCH = 8051


[C8051T601]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-1DFF
INSTR = CIP-51
ARCH = 8051

[C8051T602]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-FFF
INSTR = CIP-51
ARCH = 8051

[C8051T603]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-FFF
INSTR = CIP-51
ARCH = 8051

[C8051T604]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-7FF
INSTR = CIP-51
ARCH = 8051

[C8051T605]
MAKE = SILABS
INTRAM = 100
XRAM =  0-0
ROM = 0-7FF
INSTR = CIP-51
ARCH = 8051

[C8051T610]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-3DFF
INSTR = CIP-51
ARCH = 8051

[C8051T616]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-3DFF
INSTR = CIP-51
ARCH = 8051


[C8051T617]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-3DFF
INSTR = CIP-51
ARCH = 8051


[C8051T612]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-1FFF
INSTR = CIP-51
ARCH = 8051

[C8051T613]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-1FFF
INSTR = CIP-51
ARCH = 8051


[C8051T614]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-1FFF
INSTR = CIP-51
ARCH = 8051

[C8051T615]
MAKE = SILABS
INTRAM = 100
XRAM =  0-3FF
ROM = 0-1FFF
INSTR = CIP-51
ARCH = 8051

[C868_1R]
MAKE = INFINEON
INTRAM = 100
XRAM = FF00-FFFF
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# has 4K of Boot/self test ROM also

[C868_1S]
MAKE = INFINEON
INTRAM = 100
XRAM = FF00-FFFF
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# has 4K of Boot/self test ROM also

[CC1010]
MAKE = CHIPCON
INTRAM = 80
XRAM = 0-7FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# has additional instruction TRAP (A5) used for dubugging purposes.
# dual data pointer.

[CC1110]
MAKE = CHIPCON
INTRAM = 100
XRAM = F000-FEFF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer.
# internal RAM accessable via MOVX/DMA at addresses FF00-FFFF.
# SFRs and other registers accessable via MOVX/DMA at DF00-DFFF.

[CC1110F8] 
MAKE = CHIPCON
INTRAM = 100
XRAM = F000-F2FF
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051

[CC1110F16] 
MAKE = CHIPCON
INTRAM = 100
XRAM = F000-F6FF
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[CC1110F32] 
MAKE = CHIPCON
INTRAM = 100
XRAM = F000-FEFF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[CC1111F8] 
MAKE = CHIPCON
INTRAM = 100
XRAM = F000-F2FF
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051

[CC1111F16] 
MAKE = CHIPCON
INTRAM = 100
XRAM = F000-F6FF
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[CC1111F32] 
MAKE = CHIPCON
INTRAM = 100
XRAM = F000-FEFF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[CC2430F128]
MAKE = CHIPCON
INTRAM = 100
XRAM = E000-FFFF
OFFRAM = 0-FFFF
ROM = 0-FFFF
BANKROM = 8000-1FFFF
BANKADR = 8000-FFFF
BANKTYPE = H
INSTR = MCS-51
ARCH = 8051
# MPAGE register holds upper address of MOVX

[CC2430F32]
MAKE = CHIPCON
INTRAM = 100
XRAM = E000-FFFF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# MPAGE register holds upper address of MOVX

[CC2430F64]
MAKE = CHIPCON
INTRAM = 100
XRAM = E000-FFFF
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# MPAGE register holds upper address of MOVX

[COM20051]
MAKE = SMSC
INTRAM = 100
OFFRAM = 0-FFFE
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# chip has relocatable set of registers for ARCNET.
# user should define the symbol ARCNETADDRESS with the value of the start address of ARCNET registers
# if undefined, this will default to 0.
# WARNING: this definition does not load the ADDRESSDECODE register (@ 0xFFFF), user's code MUST do this also.
# The ARCNET register address range (in external data) MUST also be reserved by the user with command options.

[COM20051I]
MAKE = SMSC
INTRAM = 100
OFFRAM = 0-FFFE
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# chip has relocatable set of registers for ARCNET.
# user should define the symbol ARCNETADDRESS with the value of the start address of ARCNET registers
# if undefined, this will default to 0.
# WARNING: this definition does not load the ADDRESSDECODE register (@ 0xFFFF), user's code MUST do this also.
# The ARCNET register address range (in external data) MUST also be reserved by the user with command options.

[CMX850]
MAKE = CML
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# can bank program memory, but this banking scheme must be defined in user code.
# Can enter a mode where program can execute from XRAM.

[CY7C68013]
MAKE = CYPRESS
INTRAM = 100
XRAM = 0-1FFF,E000-E1FF
OFFRAM = 2000-DFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# RAM also exists from E200-FFF - USB regs and buffers

[DMC8031]
MAKE = DAEWOO
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[DMC8032]
MAKE = DAEWOO
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[DMC8051]
MAKE = DAEWOO
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[DMC8052]
MAKE = DAEWOO
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[DS2250T_32]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF

[DS2250T_64]
MAKE = DALLAS
INTRAM = 80
XRAM = 8000-FFFF
OFFRAM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF
# note external data range

[DS2250T_8]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-1FFF

[DS2250_32]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF

[DS2250_64]
MAKE = DALLAS
INTRAM = 80
XRAM = 8000-FFFF
OFFRAM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF
# note external data range

[DS2250_8]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-1FFF

[DS2251T_128]
MAKE = DALLAS
INTRAM = 80
XRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# data/program memory are separate 64k blocks, no external memory expansion available

[DS2251T_32]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF
# data/program memory is partitioned in 32K block

[DS2251T_64]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-FFFF

[DS2252T_128]
MAKE = DALLAS
INTRAM = 80
XRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# DS2252T disallows off-chip program memory

[DS2252T_32]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# DS2252T disallows off-chip program memory
# OFFROM entires just provide boundaries for user to abide by
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF

[DS2252T_64]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# DS2252T disallows off-chip program memory
# OFFROM entires just provide boundaries for user to abide by
# non-volatile RAM range code/data partionable by bootloader is 0-FFFF

[DS5000FP]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-1FFF
# 0-30h of program memory is vector RAM.

[DS5000T_32]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF

[DS5000T_8]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-1FFF

[DS5000_32]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF

[DS5000_8]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-1FFF

[DS5001FP]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-FFFF
# 0-30h of program memory is vector RAM

[DS5002FP]
MAKE = DALLAS
INTRAM = 80
XRAM = 0-FFFF
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# 0-30h of program memory is vector RAM
# DS5002FP disallows off-chip program memory

[DS80C310]
MAKE = DALLAS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable speed MOVX instruction

[DS80C320]
MAKE = DALLAS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable speed MOVX instruction

[DS80C323]
MAKE = DALLAS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable speed MOVX instruction

[DS80C390]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-FFF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51+modified
ARCH = 8051
#ARCH = 80C400
# 22 bit prog/data conter (extended mem access up to 4MB!), has 512b CAN message centre
# note: this chip can PARTITION program/data from 0,FFF

[DS80C400]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-23FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51+modified
ARCH = 8051
#ARCH = 80C400
# has 4 data pointers, each can enable auto increment feature.
# has 3 modes of addressing data/program:
# 16-bit mode is supported (default)
# 24-bit paged is not supported as entire pages of 64k are swapped at once
# 24-bit contiguous is not supported
# the on-chip RAM can be mapped to a different address via SFR settings.
# also has 256 bytes of RAM for CAN registers from DB00-DBFF.

[DS80C410]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-FFFF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51+modified
ARCH = 8051
#ARCH = 80C400
# has 4 data pointers, each can enable auto increment/decrement feature.
# can enable A5 instruction as software breakpoint
# has 3 modes of addressing data/program:
# 16-bit mode is supported (default)
# 24-bit paged is not supported as entire pages of 64k are swapped at once
# 24-bit contiguous is not supported
# the on-chip RAM can be mapped to a different address via SFR settings.
# also has 256 bytes of RAM for CAN registers from FFDB00-FFDBFF.
# also has SRAM from FFDC00-FFFFFF.

[DS80C411]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-FFFF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51+modified
ARCH = 8051
#ARCH = 80C400
# has 4 data pointers, each can enable auto increment/decrement feature.
# can enable A5 instruction as software breakpoint
# has 3 modes of addressing data/program:
# 16-bit mode is supported (default)
# 24-bit paged is not supported as entire pages of 64k are swapped at once
# 24-bit contiguous is not supported
# the on-chip RAM can be mapped to a different address via SFR settings.
# also has 256 bytes of RAM for CAN registers from FFDB00-FFDBFF.
# also has SRAM from FFDC00-FFFFFF.

[DS83C520]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable speed MOVX instruction, ROMSIZE feature
# has 4 diff memory conditions, each with diff address ranges

[DS83C530]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# ROMSIZE feature
# has 4 diff memory conditions, each with diff address ranges

[DS87C520]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable speed MOVX instruction, ROMSIZE feature
# has 4 diff memory conditions, each with diff address ranges

[DS87C530]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# ROMSIZE feature
# has 4 diff memory conditions, each with diff address ranges

[DS87C550]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-03FF
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# ROMSIZE feature

[DS89C420]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# also has page mode, Programmable while in-application:
# program memory divided into 2 programmable flash banks(0-1FFF,2000-3FFF).

[FHG8051]
MAKE = FRAUNHOFER
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# synthesizeable microcontroller core

[FIPSOC]
MAKE = SIDSA
INTRAM = 100
XRAM = FF00-FFFF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has 512 bytes of boot memory from address 0.
# Care must be taken when using HW probing area or PL Block,
# not to interfere with data in same address range. 

[GC80C520A0]
MAKE = GENCORE
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51+decDPTR(A5)
ARCH = 8051
# implements a dec DPTR instruction (A5h)
# P2 (upper address) can be read from AUXAD alternately

[GC80C520G0]
MAKE = GENCORE
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51+decDPTR(A5)
ARCH = 8051
# implements a dec DPTR instruction (A5h)
# P2 (upper address) can be read from AUXAD alternately

[GC81C510A0]
MAKE = GENCORE
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 1000-FFFF
INSTR = MCS-51+decDPTR(A5)
ARCH = 8051
# implements a dec DPTR instruction (A5h)
# P2 (upper address) can be read from AUXAD alternately

[GC81C510A1]
MAKE = GENCORE
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 2000-FFFF
INSTR = MCS-51+decDPTR(A5)
ARCH = 8051
# implements a dec DPTR instruction (A5h)
# P2 (upper address) can be read from AUXAD alternately

[GC81C520A0]
MAKE = GENCORE
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 2000-FFFF
INSTR = MCS-51+decDPTR(A5)
ARCH = 8051
# implements a dec DPTR instruction (A5h)
# P2 (upper address) can be read from AUXAD alternately

[GC81C520G0]
MAKE = GENCORE
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 2000-FFFF
INSTR = MCS-51+decDPTR(A5)
ARCH = 8051
# implements a dec DPTR instruction (A5h)
# P2 (upper address) can be read from AUXAD alternately

[GC81C591A0]
MAKE = GENCORE
INTRAM = 100
XRAM = 0-6FF
OFFRAM = 0700-F7FF
ROM = 0-FFFF
INSTR = MCS-51+decDPTR(A5)
ARCH = 8051
# implements a dec DPTR instruction (A5h)
# P2 (upper address) can be read from AUXAD alternately

[GC81C591G0]
MAKE = GENCORE
INTRAM = 100
XRAM = 0-6FF
OFFRAM = 0700-F7FF
ROM = 0-FFFF
INSTR = MCS-51+decDPTR(A5)
ARCH = 8051
# implements a dec DPTR instruction (A5h)
# P2 (upper address) can be read from AUXAD alternately

[GC87C510A0]
MAKE = GENCORE
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 1000-FFFF
INSTR = MCS-51+decDPTR(A5)
ARCH = 8051
# implements a dec DPTR instruction (A5h)
# P2 (upper address) can be read from AUXAD alternately

[GC87C510A1]
MAKE = GENCORE
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 1000-FFFF
INSTR = MCS-51+decDPTR(A5)
ARCH = 8051
# implements a dec DPTR instruction (A5h)
# P2 (upper address) can be read from AUXAD alternately

[GC87C520A0]
MAKE = GENCORE
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 2000-FFFF
INSTR = MCS-51+decDPTR(A5)
ARCH = 8051
# implements a dec DPTR instruction (A5h)
# P2 (upper address) can be read from AUXAD alternately

[GC87C520G0]
MAKE = GENCORE
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 2000-FFFF
INSTR = MCS-51+decDPTR(A5)
ARCH = 8051
# implements a dec DPTR instruction (A5h)
# P2 (upper address) can be read from AUXAD alternately

[GC89C591A0]
MAKE = GENCORE
INTRAM = 100
XRAM = 0-06FF
OFFRAM = 0700-F7FF
ROM = 0-FFFF
INSTR = MCS-51+decDPTR(A5)
ARCH = 8051
# implements a dec DPTR instruction (A5h)
# P2 (upper address) can be read from AUXAD alternately

[GC89C591G0]
MAKE = GENCORE
INTRAM = 100
XRAM = 0-06FF
OFFRAM = 0700-F7FF
ROM = 0-FFFF
INSTR = MCS-51+decDPTR(A5)
ARCH = 8051
# implements a dec DPTR instruction (A5h)
# P2 (upper address) can be read from AUXAD alternately

[GMS90C31]
MAKE = HYNIX
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90C32]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90C320]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90C51]
MAKE = HYNIX
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90C52]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90C54]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90C56]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-5FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90C58]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L31]
MAKE = HYNIX
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L32]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L320]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L51]
MAKE = HYNIX
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L52]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L54]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L56]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-5FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L58]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C1051]
MAKE = HYNIX
INTRAM = 40
ROM = 0-03FF
INSTR = MCS-51
ARCH = 80C751

[GMS97C2051]
MAKE = HYNIX
INTRAM = 80
ROM = 0-07FF
INSTR = MCS-51
ARCH = 80C751

[GMS97C51]
MAKE = HYNIX
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C51H]
MAKE = HYNIX
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C52]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C52H]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C54]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C54H]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C56]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-5FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C56H]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-5FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C58]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C58H]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97L1051]
MAKE = HYNIX
INTRAM = 40
ROM = 0-03FF
INSTR = MCS-51
ARCH = 80C751

[GMS97L2051]
MAKE = HYNIX
INTRAM = 80
ROM = 0-07FF
INSTR = MCS-51
ARCH = 80C751

[GMS97L51]
MAKE = HYNIX
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97L52]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97L54]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97L56]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-5FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97L58]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS99C58]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[HMS91C7132]
MAKE = HYNIX
INTRAM = 100
XRAM = 0-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# (RESTRCTED USE OF MOVX INST 92)
# The XRAM is enabled by default, but may be diasabled via sfr bit EXCON.0

[HMS91C7134]
MAKE = HYNIX
INTRAM = 100
XRAM = 0-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# (RESTRICTED USE OF MOVX INST 92)
# The XRAM is enabled by default, but may be diasabled via sfr bit EXCON.0

[HMS91C8032]
MAKE = HYNIX
INTRAM = 100
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# this chip claims to have 1K data RAM. This is because lower internal memory is banked - we do not support.

[HMS91C8108]
MAKE = HYNIX
INTRAM = 100
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# this chip can expand its internal RAM with paging, this is not yet supported.

[HMS91C8116]
MAKE = HYNIX
INTRAM = 100
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# this chip can expand its internal RAM with paging, this is not yet supported.

[HMS91C8132]
MAKE = HYNIX
INTRAM = 100
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# this chip can expand its internal RAM with paging, this is not yet supported.

[HMS97C7132]
MAKE = HYNIX
INTRAM = 100
XRAM = 0-00FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# (RESTRICTED USE OF MOVX INSTR 92)
# XRAM is available by default, but can be disabled via EXCON sfr.

[HMS97C7134]
MAKE = HYNIX
INTRAM = 100
XRAM = 0-00FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# (RESTRICTED USE OF MOVX INSTR 92)
# XRAM is available by default, but can be disabled via EXCON sfr.

[HMS97C8032]
MAKE = HYNIX
INTRAM = 100
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# this chip claims to have 1K data RAM. This is because lower internal memory is banked - we do not support.

[HMS97C8132]
MAKE = HYNIX
INTRAM = 100
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# this chip can expand its internal RAM with paging, this is not yet supported.

[HT83C51FX]
MAKE = HONEYWELL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IA8044]
MAKE = INNOVASIC
INTRAM = C0
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IA80C152]
MAKE = INNOVASIC
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IA8344]
MAKE = INNOVASIC
INTRAM = C0
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80C31]
MAKE = ICSI
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80C32]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80C51]
MAKE = ICSI
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80C52]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80C54]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80C58]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80LV31]
MAKE = ICSI
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80LV32]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80LV51]
MAKE = ICSI
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80LV52]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC89C51A]
MAKE = ICSI
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC89C52A]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80C31]
MAKE = ISSI
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80C32]
MAKE = ISSI
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80C51]
MAKE = ISSI
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80C52]
MAKE = ISSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80LV31]
MAKE = ISSI
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80LV32]
MAKE = ISSI
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80LV51]
MAKE = ISSI
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80LV52]
MAKE = ISSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS89C52]
MAKE = ISSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS89E54]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has AUXRAM at 0-01FF, disabled by default, enabled via SFR
# E series are flash parts

[IS89E58]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has AUXRAM at 0-01FF, disabled by default, enabled via SFR
# E series are flash parts

[IS89E64]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-EFFF,F000-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has AUXRAM at 0-01FF, disabled by default, enabled via SFR
# E series are flash parts, E64 has 2 blocks - may be erased independently

[KS152JB]
MAKE = KAWASAKI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# do not write to PORT 0 if external memory is used

[LPC47N252]
MAKE = SMSC
INTRAM = 100
XRAM = 0-FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH =  8051
# has MPAGE register which can be used during MOVX instruction

[LZ87010]
MAKE = SHARP
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = enhanced MCS-51
ARCH = 8051
# has 2 added instructions mapped in the unused 0xA5 position (TRAP and MOVC@(DPTR++),A)

[M6759]
MAKE = ACER
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 64k internal flash, also supports additional 64k ROM
# XRAM can be disabled via SFR

[M8051EWARP]
MAKE = MENTOR
INTRAM = 100
XRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51+A5
ARCH = 8051
# additional instructions are implimented in the unused A5 position
# Has SFR E0 which may be reloacated to another address. Default address is A2h.
# External SFRs (ESFRs) may be implimented. They can occupy any address between 80-FF,
# (directly addressable) that has not yet occupied.
# An ESFR may be bit addressable if they are in C0,C8 or D8.

[MAX7651]
MAKE = MAXIM
INTRAM = 100
OFFRAM = 0100-FFFF
ROM = 0-3FBF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# ROM area 3FC0-3FFF is reserved on-chip, Address range may be utilised only if EA is 1
# on-chip program memory is flash, divided into 2 blocks

[MAX7652]
MAKE = MAXIM
INTRAM = 100
OFFRAM = 0100-FFFF
ROM = 0-1FFF,2000-3FBF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# ROM area 3FC0-3FFF is reserved on-chip, Address range may be utilised only if EA is 1
# on-chip program memory is flash, divided into 2 blocks

[MPC89E515A]
MAKE = MEGAWIN
INTRAM = 100
XRAM = 0-03FF
OFFRAM = 0-FFFF
ROM = 0-FBFF
INSTR = MCS-51
ARCH = 8051
# Off-chip RAM enabled by setting ERAM bit in SFR
# partition between AP-memory and ISP-memory can be moved between 0xEC00 and 0xFBFF

[MPC89E51A]
MAKE = MEGAWIN
INTRAM = 100
XRAM = 0-00FF
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip RAM enabled by setting ERAM bit in SFR

[MPC89E52A]
MAKE = MEGAWIN
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip RAM enabled by setting ERAM bit in SFR

[MPC89E53A]
MAKE = MEGAWIN
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-3BFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip RAM enabled by setting ERAM bit in SFR
# partition between AP-memory and ISP-memory can be moved between 0x2C00 and 0x3BFF

[MPC89E54A]
MAKE = MEGAWIN
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip RAM enabled by setting ERAM bit in SFR

[MPC89E58A]
MAKE = MEGAWIN
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip RAM enabled by setting ERAM bit in SFR

[MPC89L515A]
MAKE = MEGAWIN
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-FBFF
INSTR = MCS-51
ARCH = 8051
# Off-chip RAM enabled by setting ERAM bit in SFR
# partition between AP-memory and ISP-memory can be moved between 0xEC00 and 0xFBFF

[MPC89L516X2]
MAKE = MEGAWIN
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51 - modifed MOVX @Ri
ARCH = 8051
# Modification to MOVX @Ri so that it only accesses on-chip XRAM (0-FF).
# Off-chip data accessed via MOVX @DPTR

[MPC89L51A]
MAKE = MEGAWIN
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip RAM enabled by setting ERAM bit in SFR

[MPC89L52A]
MAKE = MEGAWIN
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip RAM enabled by setting ERAM bit in SFR

[MPC89L53A]
MAKE = MEGAWIN
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-3BFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip RAM enabled by setting ERAM bit in SFR
# partition between AP-memory and ISP-memory can be moved between 0x2C00 and 0x3BFF

[MPC89L54A]
MAKE = MEGAWIN
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip RAM enabled by setting ERAM bit in SFR

[MPC89L556X2]
MAKE = MEGAWIN
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51 - modified MOVX @Ri
ARCH = 8051
# Modification to MOVX @Ri so that it only accesses on-chip XRAM (0-FF).
# Off-chip data accessed via MOVX @DPTR

[MPC89L58A]
MAKE = MEGAWIN
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip RAM enabled by setting ERAM bit in SFR

[MSC1210Y2]
MAKE = TI
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 400-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# can partition code memory to increase data memory
# can reposition XRAM to 8000,8FFF to increase code memory
# also has boot flash from F800-FFFF

[MSC1210Y3]
MAKE = TI
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 400-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# can partition code memory to increase data memory
# can reposition XRAM to 8000,8FFF to increase code memory
# also has boot flash from F800-FFFF

[MSC1210Y4]
MAKE = TI
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 400-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# can partition code memory to increase data memory
# can reposition XRAM to 8000,8FFF to increase code memory
# also has boot flash from F800-FFFF

[MSC1210Y5]
MAKE = TI
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 400-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# can partition code memory to increase data memory
# can reposition XRAM to 8000,8FFF to increase code memory
# also has boot flash from F800-FFFF

[MSM80C154S]
MAKE = OKI
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[MSM80C31]
MAKE = OKI
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[MSM80C31F]
MAKE = OKI
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[MSM80C51]
MAKE = OKI
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[MSM80C51F]
MAKE = OKI
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[MSM83C154S]
MAKE = OKI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[MSM85C154HVS]
MAKE = OKI
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# piggy back chip, interesting ROM structure.

[MTP800]
MAKE = MYSON
INTRAM = 100
XRAM = 100-3FF
OFFRAM = 400-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XFRs reside in 0-FF of external data space
# chip can support external data memory up to size 64Mbit

[MTV112E]
MAKE = MYSON
INTRAM = 100
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# external RAM access restricted to XFRs on board from 0-FF

[MTV112M]
MAKE = MYSON
INTRAM = 100
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# external RAM access restricted to XFRs on board from 0-FF

[MTV212A16]
MAKE = MYSON
INTRAM = 100
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# XFRs are mapped into external memory from (00 to 7F)

[MTV212A24]
MAKE = MYSON
INTRAM = 100
XRAM = 80-FF
ROM = 0-5FFF
INSTR = MCS-51
ARCH = 8051
# XFRs are mapped into external memory from (00 to 7F)
# XRAM in external RAM 80-FF is banked (2x80h total)

[MTV212A32]
MAKE = MYSON
INTRAM = 100
XRAM = 80-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# XFRs are mapped into external memory from (00 to 7F)
# XRAM in external RAM 80-FF is banked (2x80h total)

[MTV212A32U]
MAKE = MYSON
INTRAM = 100
XRAM = 80-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# XFRs are mapped into external memory from (00 to 7F)
# XRAM in external RAM 80-FF is banked (4x80h total)

[MTV212A48U]
MAKE = MYSON
INTRAM = 100
XRAM = 80-FF
ROM = 0-BFFF
INSTR = MCS-51
ARCH = 8051
# XFRs are mapped into external memory from (00 to 7F)
# XRAM in external RAM 80-FF is banked (4x80h total)

[MTV212A64U]
MAKE = MYSON
INTRAM = 100
XRAM = 80-FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XFRs are mapped into external memory from (00 to 7F)
# XRAM in external RAM 80-FF is banked (6x80h total)

[MTV212M16]
MAKE = MYSON
INTRAM = 100
XRAM = 80-FF
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# XFRs are mapped into external memory from (00 to 7F)

[MTV212M24]
MAKE = MYSON
INTRAM = 100
XRAM = 80-FF
ROM = 0-5FFF
INSTR = MCS-51
ARCH = 8051
# XFRs are mapped into external memory from (00 to 7F)
# XRAM in external RAM 80-FF is banked (2x80h total)

[MTV212M32U]
MAKE = MYSON
INTRAM = 100
XRAM = 80-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# XFRs are mapped into external memory from (00 to 7F)
# XRAM in external RAM 80-FF is banked (2x80h total)

[MTV212M32]
MAKE = MYSON
INTRAM = 100
XRAM = 80-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# XFRs are mapped into external memory from (00 to 7F)
# XRAM in external RAM 80-FF is banked (4x80h total)

[MTV212M48U]
MAKE = MYSON
INTRAM = 100
XRAM = 80-FF
ROM = 0-BFFF
INSTR = MCS-51
ARCH = 8051
# XFRs are mapped into external memory from (00 to 7F)
# XRAM in external RAM 80-FF is banked (4x80h total)

[MTV212M64U]
MAKE = MYSON
INTRAM = 100
XRAM = 80-FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XFRs are mapped into external memory from (00 to 7F)
# XRAM in external RAM 80-FF is banked (6x80h total)

[MTV230M]
MAKE = MYSON
INTRAM = 100
XRAM = 0800-0AFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XFRs mapped into external memory (F00-FFF)

[MTV412M]
MAKE = MYSON
INTRAM = 100
XRAM = 800-8FF,900-9FF,E00-EFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XFRs from F00-FFF
# XRAM 900-9FF and E00-EFF are regions of dual port RAM.
# program memory is 128K flash.

[NRF24E1]
MAKE = NORDIC
INTRAM = 100
ROM = 0-0FFF,8000-81FF
INSTR = MCS-51
ARCH = 8051
# Can bank XDATA via MPAGE register
# Bootloader memory exists from 8000-81FF
# On chip program memory can be accessed as XRAM

[NRF24E2]
MAKE = NORDIC
INTRAM = 100
ROM = 0-0FFF,8000-81FF
INSTR = MCS-51
ARCH = 8051
# Can bank XDATA via MPAGE register
# Bootloader memory exists from 8000-81FF
# On chip program memory can be accessed as XRAM

[NRF9E5]
MAKE = NORDIC
INTRAM = 100
ROM = 0-0FFF,8000-81FF
INSTR = MCS-51
ARCH = 8051
# Can bank XDATA via MPAGE register
# Bootloader memory exists from 8000-81FF
# On chip program memory can be accessed as XRAM

[OM5202]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[OM5232]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[OM5234]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[OM5238]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[OM5284]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Datasheet inconsistency: ROM either 6K or 16K

[P51]
MAKE = CYBERNETIC
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51+breakpoint(E5)
ARCH = 8051
# extra instruction, has dedicated program RAM, has dual port RAM

[P80C31X2]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C31]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C32X2]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C32]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C451]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C51X2]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C51]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C51FA]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C51RA]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM 0-FF is enabled by default, disabled via SFR to make OFFRAM 0-FFFF

[P80C52X2]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C52]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C528]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# off-chip data area 0,FF seems inaccessable

[P80C54X2]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C54]
MAKE = PHILIPS
INTRAM = 100 
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C550]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# note that for this part to operate properly, pin EA must be held low

[P80C552]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C554]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM 0-FF is enabled by default, disabled via SFR to make OFFRAM 0-FFFF

[P80C557E4]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P80C557E6]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-4FF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P80C557E8]
MAKE = PHILIPS
INTRAM = 100 
XRAM = 0-6FF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P80C562]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C575]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C58X2]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C58]
MAKE = PHILIPS
INTRAM = 100 
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C592]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# this chip cannot access OFFRAM 0-FF

[P80C598]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C652]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80C851]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# also has 256 bytes of EEPROM

[P80CE558]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P80CE559]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-4FF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P80CE560]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P80CE598]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# this chip cannot access OFFRAM 0-FF

[P80CL31]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80CL410]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80CL51]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P80CL580]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C055]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# this MTV device also has 128 bytes of display RAM.

[P83C145]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-2FFF
INSTR = MCS-51
ARCH = 8051
# this MTV device also has 128 bytes of display RAM.

[P83C180]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[P83C266]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
ROM = 0-5FFF
INSTR = MCS-51
ARCH = 8051

[P83C270]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
ROM = 0-5FFF
INSTR = MCS-51
ARCH = 8051

[P83C280]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
ROM = 0-5FFF
INSTR = MCS-51
ARCH = 8051

[P83C366]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[P83C370]
MAKE = PHILIPS
INTRAM = 100 
XRAM = 0-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[P83C380]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[P83C434]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-0FFF
INSTR = MCS-51
ARCH = 8051

[P83C451]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C453]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C508]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C51FA]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C51FB]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C51FC]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C51RA]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM 0-FF is enabled by default, disabled via SFR to make OFFRAM 0-FFFF

[P83C51RB]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM 0-FF is enabled by default, disabled via SFR to make OFFRAM 0-FFFF

[P83C51RC]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM 0-FF is enabled by default, disabled via SFR to make OFFRAM 0-FFFF

[P83C51RD]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM 0-2FF is enabled by default, disabled via SFR to make OFFRAM 0-FFFF

[P83C524]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# when security bit is set, MOVC in external memory cannot access internal memory
# if on-chip ROM enabled (EA=1), region 4000-7FFF is inaccessable

[P83C528]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# off-chip data area 0,FF seems inaccessable

[P83C550]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C552]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C554]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM 0-FF is enabled by default, disabled via SFR to make OFFRAM 0-FFFF

[P83C557E4]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P83C557E6]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-4FF
OFFRAM = 0-FFFF
ROM = 0-CFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P83C557E8]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P83C562]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C566]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
ROM = 0-CFFF
INSTR = MCS-51
ARCH = 8051

[P83C570]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
ROM = 0-CFFF
INSTR = MCS-51
ARCH = 8051

[P83C575]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C576]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C591]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# this chip cannot access OFFRAM 0-FF

[P83C592]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# this chip cannot access OFFRAM 0-FF

[P83C598]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C652]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C654]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# when security bit is set, MOVC in external memory cannot access internal memory

[P83C748]
MAKE = PHILIPS
INTRAM = 40
ROM = 0-7FF
INSTR = MCS-51 without MOVX
ARCH = 80C751

[P83C749]
MAKE = PHILIPS
INTRAM = 40
ROM = 0-7FF
INSTR = reduced MCS-51
ARCH = 80C751

[P83C750]
MAKE = PHILIPS
INTRAM = 40
ROM = 0-3FF
INSTR = reduced MCS-51
ARCH = 80C751

[P83C751]
MAKE = PHILIPS
INTRAM = 40
ROM = 0-7FF
INSTR = reduced MCS-51
ARCH = 80C751

[P83C752]
MAKE = PHILIPS
INTRAM = 40
ROM = 0-7FF
INSTR = reduced MCS-51
ARCH = 80C751

#[P83C754]
#MAKE = PHILIPS
#INTRAM = 100
#ROM = 0,FFF
#INSTR = reduced MCS-51
#ARCH = CONFLICT
# Conflict in ARCH, has reduced instruction set, yet address range is too large.

[P83C766]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C770]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83C834]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051

[P83C845]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# this MTV device also has 128 bytes of display RAM.

[P83C851]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# also has 256 bytes of EEPROM

[P83C880]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051

[P83CE558]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P83CE559]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-4FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P83CE560]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P83CE598]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# this chip cannot access OFFRAM 0-FF

[P83CE654]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# when security bit is set, MOVC in external memory cannot access internal memory

[P83CL410]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83CL580]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-17FF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83CL781]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83CL782]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P83CL882]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-FFF
INSTR = reduced MCS-51
ARCH = 8051
# Conflict in ARCH, no MOVX instr by program memory is greater than 800h
# no MOVX

[P83CL883]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-1FFF
INSTR = reduced MCS-51
ARCH = 8051
# no MOVX instruction

[P83CL884]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-1FFF
INSTR = reduced MCS-51
ARCH = 8051
# no MOVX instruction
# has 128 bytes EEPROM

[P87C055]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# this MTV device also has 128 bytes of display RAM.

[P87C380]
MAKE = PHILIPS
INTRAM = 100 
XRAM = 0-FF
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[P87C451]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C453]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C508]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# when security bit is set, MOVC in external memory cannot access internal memory

[P87C51X2]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C51]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C51FA]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C51FB]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C51FC]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C51MB2]
MAKE = PHILIPS
INTRAM = 100 
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51 plus A5h
ARCH = 8051
# 16-bit addresses 64k or 23-bit address bus to 1G.
# uses instruction A5 to tell core next istruction is from expanded set.
# also has 1024 bytes of ERAM

[P87C51MC2]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51 plus A5h
ARCH = 8051
# 16-bit addresses 64k or 23-bit address bus to 1G.
# uses instruction A5 to tell core next istruction is from expanded set.
# also has 1024 bytes of ERAM

[P87C51RA]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM 0-FF is enabled by default, disabled via SFR to make OFFRAM 0-FFFF

[P87C51RB]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM 0-FF is enabled by default, disabled via SFR to make OFFRAM 0-FFFF

[P87C51RC]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM 0-FF is enabled by default, disabled via SFR to make OFFRAM 0-FFFF

[P87C51RD]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 300-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM 0-2FF is enabled by default, disabled via SFR to make OFFRAM 0-FFFF

[P87C52X2]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C52]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C524]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# when security bit is set, MOVC in external memory cannot access internal memory
# if on-chip ROM enabled (EA=1), region 4000-7FFF is inaccessable

[P87C528]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# off-chip data area 0,FF seems inaccessable

[P87C54X2]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C54]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C550]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C552]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C554]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM 0-FF is enabled by default, disabled via SFR to make OFFRAM 0-FFFF

[P87C557E8]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P87C575]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C576]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C58X2]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C58]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C591]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# this chip cannot access OFFRAM 0-FF

[P87C652]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C654]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C748]
MAKE = PHILIPS
INTRAM = 40
ROM = 0-7FF
INSTR = reduced MCS-51
ARCH = 80C751

[P87C749]
MAKE = PHILIPS
INTRAM = 40
ROM = 0-7FF
INSTR = reduced MCS-51
ARCH = 80C751

[P87C750]
MAKE = PHILIPS
INTRAM = 40
ROM = 0-3FF
INSTR = reduced MCS-51
ARCH = 80C751

[P87C751]
MAKE = PHILIPS
INTRAM = 40
ROM = 0-7FF
INSTR = reduced MCS-51
ARCH = 80C751

[P87C752]
MAKE = PHILIPS
INTRAM = 40
ROM = 0-7FF
INSTR = reduced MCS-51
ARCH = 80C751

#[P87C754]
#MAKE = PHILIPS
#INTRAM = 100
#ROM = 0,FFF
#INSTR = reduced MCS-51
#ARCH = CONFLICT
# Conflict in ARCH, has reduced instruction set, yet address range is too large.

[P87C766]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87C770]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P87CE560]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P87CL881H]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
OFFRAM = 0-FFFF
ROM = 0-FBFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# AUXRAM enabled by default, may be disabled via SFR

[P87CL883]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-1FFF
INSTR = reduced MCS-51
ARCH = 8051
# no MOVX instruction

[P87CL884]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-1FFF
INSTR = reduced MCS-51
ARCH = 8051
# no MOVX instruction
# has 128 bytes EEPROM

[P87CL888]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-1FFF
INSTR = reduced MSC-51
ARCH = 8051
# has test array built into Prog.mem 8000-81FF
# no external memory allowed. MOVX operations can't be used.

[P87LPC760]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-3FF,FCE0-FCFF
INSTR = MCS-51
ARCH = 8051
# has 32 bytes for serials etc from FCE0-FCFF

[P87LPC761]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-7FF,FCE0-FCFF
INSTR = MCS-51
ARCH = 8051
# has 32 bytes for serials etc from FCE0-FCFF

[P87LPC762]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-7FF,FCE0-FCFF
INSTR = MCS-51
ARCH = 8051
# 32b ROM from FCE0 for serial number, not code
# has 2 config bytes in data FD00,FD01

[P87LPC764]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-FFF,FCE0-FCFF
INSTR = MCS-51
ARCH = 8051
# 32b ROM from FCE0 for serial number, not code
# has 2 config bytes in data FD00,FD01

[P87LPC767]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-FFF,FCE0-FCFF
INSTR = MCS-51
ARCH = 8051
# 32b ROM from FCE0 for serial number, not code
# has 2 config bytes in data FD00,FD01

[P87LPC768]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-FFF,FCE0-FCFF
INSTR = MCS-51
ARCH = 8051
# 32b ROM from FCE0 for serial number, not code
# has 2 config bytes in data FD00,FD01

[P87LPC769]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-FFF,FCE0-FCFF
INSTR = MCS-51
ARCH = 8051
# 32b ROM from FCE0 for serial number, not code
# has 2 config bytes in data FD00,FD01

[P89C51RA2XX]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled by setting EXTRAM bit in SFRs
# has boot ROM in FC00-FFFF

[P89C51RB2HXX]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled by setting EXTRAM bit in SFRs

[P89C51RB2XX]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled by setting EXTRAM bit in SFRs
# has boot ROM in FC00-FFFF

[P89C51RC2HXX]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled by setting EXTRAM bit in SFRs

[P89C51RC2XX]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled by setting EXTRAM bit in SFRs
# has boot ROM in FC00-FFFF

[P89C51RD2HXX]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled by setting EXTRAM bit in SFRs

[P89C51RD2XX]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled by setting EXTRAM bit in SFRs
# has boot ROM in FC00-FFFF

[P89C51]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P89C51RB2]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# ERAM (XRAM) may be disabled via SFR

[P89C51RC]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P89C51RC2]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P89C51RD]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P89C51RD2]
MAKE = PHILIPS
INTRAM = 100 
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P89C51X2]
MAKE = PHILIPS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P89C52]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P89C52X2]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P89C535]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip data 0-FF is not possible

[P89C536]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip data 0-FF is not possible

[P89C538]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip data 0-FF is not possible

[P89C54]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P89C54X2]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P89C557E4]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 300-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P89C58]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P89C58X2]
MAKE = PHILIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[P89C60X2]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR

[P89C61X2]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR

[P89C660]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip data 0-FF is not possible

[P89C662]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 300-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip data 0-2FF is not possible

[P89C664]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip data 0-6FF is not possible

[P89C668]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip data 0-1FFF is not possible

[P89C669]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51 plus A5h
ARCH = 8051
# 16-bit addresses 64k or 23-bit address bus to 1G.
# impliments the A5h instruction, headerfile defines this in a macro: MXE()

[P89C738]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip data 0-FF is not possible

[P89C739]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Off-chip data 0-FF is not possible

[P89CE558]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# EXTRAM enabled by default, disabled via SFR

[P89LPC901]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[P89LPC902]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[P89LPC903]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[P89LPC906]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[P89LPC907]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[P89LPC908]
MAKE = PHILIPS
INTRAM = 80
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[P89LPC915]
MAKE = NXP
INTRAM = 100
ROM = 0-7FF
INSTR = MCS-51
ARCH = 8051
# dual data pointers

[P89LPC916]
MAKE = NXP
INTRAM = 100
ROM = 0-7FF
INSTR = MCS-51
ARCH = 8051
# dual data pointers

[P89LPC917]
MAKE = NXP
INTRAM = 100 
ROM = 0-7FF
INSTR = MCS-51
ARCH = 8051
# dual data pointers

[P89LPC920]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-7FF
INSTR = MCS-51
ARCH = 8051
# has boot memory FF00-FFFF
# dual data pointers

[P89LPC921]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-FFF
INSTR = MCS-51
ARCH = 8051
# has boot memory FF00-FFFF
# dual data pointers

[P89LPC922]
MAKE = PHILIPS
INTRAM = 100 
ROM = 0-1FF
INSTR = MCS-51
ARCH = 8051
# has boot memory FF00-FFFF
# dual data pointers

[P89LPC930]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-FFF
INSTR = MCS-51
ARCH = 8051
# dual data pointers

[P89LPC931]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# dual data pointers

[P89LPC932]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
OFFRAM = 200-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has 512 bytes of on chip EEPROM
# Has dual data pointer

[P89LPC933]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-FFF
INSTR = MCS-51
ARCH = 8051

[P89LPC934]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051

[P89LPC935]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# also has 512 bytes of EEPROM accessable via SFRS

[P89LPC936]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# also has 512 bytes of EEPROM accessable via SFRS

[PAGEONE]
MAKE = WINEDGE
INTRAM = 100
XRAM = 0-FFFF
ROM = 0-FFFF
BANKROM = C000-FFFFF
BANKADR = C000-FFFF
BANKTYPE = G
INSTR = NON STANDARD
ARCH = 8051
# some instructions have been replaced with new ones
# we do not support the banked internal memory scheme used on this chip.
# This chip has 4 independent banking windows, 3 can access 1 of 255 banks.
# The other window can access 1 of 7.
# This setting has enabled only the uppermost of these windows.
# Each window can be configured to point to ROM/RAM/IO, however we do not
# support this feature.
# We presently do not support banks 0,1 & 2 appearing in bank window. 

[PCD6001]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
#BANKADR = 0,FFFF
#BANKTYPE = P
INSTR = MCS-51
ARCH = 8051
# DSP on chip, massive external data access (512k)
# XRAM can be disabled via SFR bit (ARD)

[PL_ONE]
MAKE = DOMOSYS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# program memory can be expanded further with bank switching,
# however no details of how this is done can be found.

[R8032S]
MAKE = RDC
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[R8032TTEX]
MAKE = RDC
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable length MOVX instruction

[R8032TTE]
MAKE = RDC
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable length MOVX instruction

[R8032TT]
MAKE = RDC
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable length MOVX instruction

[R8032T]
MAKE = RDC
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable length MOVX instruction

[S80C552]
MAKE = SIGNETICS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[S87C552]
MAKE = SIGNETICS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SAA5290]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[SAA5290A]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[SAA5291]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[SAA5291A]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[SAA5296]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[SAA5296A]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[SAA5297]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-FFFF
INSTR =	MCS-51
ARCH = 8051

[SAA5297A]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SAA5297H]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR bit (ARD)

[SAA5491]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[SAA5491H]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR bit (ARD)

[SAA5496]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[SAA5497]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SAA5497A]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SAA5497H]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR bit (ARD)

[SAA5500]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[SAA5501]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[SAA5502]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-CFFF
INSTR = MCS-51
ARCH = 8051

[SAA5503]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SAA5520]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[SAA5521]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[SAA5522]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-CFFF
INSTR = MCS-51
ARCH = 8051

[SAA5523]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SAA5530]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[SAA5531]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[SAA5532]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-CFFF
INSTR = MCS-51
ARCH = 8051

[SAA5533]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SAA5540]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051

[SAA5541]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[SAA5542]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-CFFF
INSTR = MCS-51
ARCH = 8051

[SAA5543]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SAA5547]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-5FFF
INSTR = MCS-51
ARCH = 8051

[SAA5551]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[SAA5552]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
ROM = 0-CFFF
INSTR = MCS-51
ARCH = 8051

[SAA5553]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SAA5561]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-1FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051

[SAA5562]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-2FF
ROM = 0-CFFF
INSTR = MCS-51
ARCH = 8051

[SAA5563]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-3FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SAA5564]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-4FF
ROM = 0-FFFF
#BANKS = 0,2
BANKADR = 8000-FFFF
BANKTYPE = A
INSTR = MCS-51
ARCH = 8051
# can select between 2 ROM banks

[SAA5565]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
ROM = 0-FFFF
#BANKS = 0,3
BANKADR = 8000-FFFF
BANKTYPE = A
INSTR = MCS-51
ARCH = 8051

[SAA5645]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
ROM = 0-FFFF
#BANKS = 0,3
BANKADR = 8000-FFFF
BANKTYPE = A
INSTR = MCS-51
ARCH = 8051

[SAA5647]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
ROM = 0-FFFF
#BANKS = 0,5
BANKADR = 8000-FFFF
BANKTYPE = A
INSTR = MCS-51
ARCH = 8051

[SAA5665]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
ROM = 0-FFFF
#BANKS = 0,3
BANKADR = 8000-FFFF
BANKTYPE = A
INSTR = MCS-51
ARCH = 8051

[SAA5667]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-6FF
ROM = 0-FFFF
#BANKS = 0,5
BANKADR = 8000-FFFF
BANKTYPE = A
INSTR = MCS-51
ARCH = 8051

[SAB80515]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SAB80535]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SAB80C515]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SAB80C515A]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM from F800-FBFF and forbidden FC00-FFFF if SFR enables XRAM

[SAB80C517]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 80C517

[SAB80C517A]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 80C517
# has XRAM from F800-FFFF but is disabled by default

[SAB80C535]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SAB80C537]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 80C517

[SAB83C515A_5]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM from F800-FBFF and forbidden FC00-FFFF if SFR enables XRAM

[SAB83C517A_5]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 80C517
# has XRAM from F800-FFFF but is disabled by default

[SDA30C263]
MAKE = INFINEON
INTRAM = 100
XRAM = F800-FBFF
ROM = 0-FFFF
#BANKADR = 0,FFFF
#BANKTYPE = S
INSTR = MCS-51
ARCH = 8051

[SDA30C264]
MAKE = INFINEON
INTRAM = 100
XRAM = F800-FFFF
ROM = 0-FFFF
#BANKADR = 0,FFFF
#BANKTYPE = S
INSTR = MCS-51
ARCH = 8051

[SDA55XX]
MAKE = MICRONAS
INTRAM = 100
XRAM = C000-FFFF
OFFRAM = 0-BFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
#BANKADR = 0,FFFF
#BANKTYPE = S
INSTR = reduced MCS-51 set
ARCH = 8051
# upper 16k of memory reserved for XRAM(in all banks), external mem banks from 0-C000, 1K XRAM is reserved fo text character storage
# this bank switching process of this device is quite advanced and is not yet supported

[SM2965]
MAKE = SYNCMOS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM is enabled by default, can be disabled (via SFR)
# this will allow 0-FFFF data access off chip.

[SM5964]
MAKE = SYNCMOS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM is enabled by default, can be disabled (via SFR)
# this will allow 0-FFFF data access off chip.

[SM8051]
MAKE = SYNCMOS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SM8052]
MAKE = SYNCMOS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SM8058]
MAKE = SYNCMOS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# XRAM is enabled by default, can be disabled (via SFR)
# this will allow 0-FFFF data access off chip.

[SM89516]
MAKE = SYNCMOS
INTRAM = 100
OFFRAM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
XRAM = 0-2FF
ROM = 0-FFFF

[SM8951]
MAKE = SYNCMOS
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SM8952]
MAKE = SYNCMOS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SM8954]
MAKE = SYNCMOS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SM8958]
MAKE = SYNCMOS
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 300-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM is enabled by default, can be disabled (via SFR)
# this will allow 0-FFFF data access off chip.

[SS1102C]
MAKE = SILICONIANS
INTRAM = 100
XRAM = 0-FF
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# MSIZ feature can limit internal ROM size
# off-chip memory can be accessed if the chip is run in a special test mode.

[SS8203]
MAKE = SILICONIANS
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# MSIZ feature can limit internal ROM size

[SST89C54]
MAKE = SST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
#ROM = F000,FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# primary prog block = 0000-3FFF, secondary = F000-FFFF
# secondary block disabled by default, enabled via SFR
# has additional 4K EEPROM

[SST89C58]
MAKE = SST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
#ROM = F000,FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# primary prog block = 0000-7FFF, secondary = F000-FFFF
# secondary block disabled by default, enabled via SFR
# has additional 4K EEPROM

[SST89C59]
MAKE = SST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has additional 4K EEPROM

[SST89E52RD2]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-1FFF,E000-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SST89E52RD]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-1FFF,E000-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SST89E54RD2]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-3FFF,E000-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Note: Datasheet says 0-7FFF of flash - this is an error

[SST89E54RD]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-3FFF,E000-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Note: Datasheet says 0-7FFF of flash - this is an error

[SST89E554RC]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-7FFF,E000-FFFF
OFFROM = 0-FFFF
#BANKADR = 0,1FFF
#BANKTYPE = F
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR
# the bank window, will map physical memory E000-FFFF to address 0-1FFF

[SST89E554]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-7FFF,E000-FFFF
OFFROM = 0-FFFF
#BANKADR = 0,1FFF
#BANKTYPE = F
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR
# the bank window, will map physical memory E000-FFFF to address 0-1FFF
# Bank addresses beginning at zero are not supported

[SST89E564RD]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
#BANKADR = 0,1FFF
#BANKTYPE = F
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR
# Bank addresses beginning at zero are not supported

[SST89E564]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
#BANKADR = 0,1FFF
#BANKTYPE = F
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR
# Bank addresses beginning at zero are not supported

[SST89E58RD2]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-7FFF,E000-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SST89E58RD]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-7FFF,E000-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SST89F54]
MAKE = SST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 4K EEPROM

[SST89F58]
MAKE = SST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 4K EEPROM

[SST89V52RD2]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SST89V52RD]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SST89V54RD2]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Note: Datasheet says 0-7FFF of flash - this is an error

[SST89V54RD]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Note: Datasheet says 0-7FFF of flash - this is an error

[SST89V554RC]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-7FFF,E000-FFFF
OFFROM = 0-FFFF
#BANKADR = 0,1FFF
#BANKTYPE = F
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR
# the bank window, will map physical memory E000-FFFF to address 0-1FFF
# Bank addresses beginning at zero are not supported

[SST89V554]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-7FFF,E000-FFFF
OFFROM = 0-FFFF
#BANKADR = 0,1FFF
#BANKTYPE = F
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR
# the bank window, will map physical memory E000-FFFF to address 0-1FFF
# Bank addresses beginning at zero are not supported

[SST89V564RD]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
#BANKADR = 0,1FFF
#BANKTYPE = F
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR
# Bank addresses beginning at zero are not supported

[SST89V564]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
#BANKADR = 0,1FFF
#BANKTYPE = F
INSTR = MCS-51
ARCH = 8051
# XRAM can be disabled via SFR
# Bank addresses beginning at zero are not supported

[SST89V58RD2]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SST89V58RD]
MAKE = SST
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[SZF2002]
MAKE = PHILIPS
INTRAM = 100
XRAM = 0-17FF
OFFRAM = 1800-FFFF
ROM = 0-17FF,2000-37FF
OFFROM = 0-FFFF
#BANKS = 1,7
BANKADR = 8000-FFFF
BANKTYPE = Z
INSTR = MCS-51
ARCH = 8051
# up to 256k flash if banked, banks addressed from 8000 to FFFF
# on-chip external RAM exists between 2000-37FF
# Bank 0 is not supported in bank window.

[T33520]
MAKE = TRUMPION
INTRAM = 100
XRAM = 0-1FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# claims supports up to 384M of MP3 data
# AUXRAM may be disabled via SFR, on-chip ROM may be disabled via SFR also

[T80C154]
MAKE = TEMIC
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# chip is actually called 80C154 (no T)

[T80C5111]
MAKE = ATMEL
INTRAM = 100
ROM = 0-FFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[T80C5112]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[T83C154D]
MAKE = TEMIC
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# chip is actually called 83C154D (no T)

[T83C154]
MAKE = TEMIC
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# chip is actually called 83C154 (no T)

[T83C5101]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[T83C5102]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[T83C5111]
MAKE =  ATMEL
INTRAM = 100
ROM = 0-FFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[T83C5112]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[T83C5121]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has bootloader from C000,F7FF
# Some SFRs appear to be banked
# data is preliminary

[T85C5121]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has bootloader from C000,F7FF
# Some SFRs appear to be banked
# data is preliminary

[T87C5101]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[T87C5111]
MAKE = ATMEL
INTRAM = 100
ROM = 0-FFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[T87C5112]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[T89C5115]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# has EEPROM from 0,7FF

[T89C5121]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has bootloader from C000,F7FF
# data is preliminary
# 89 version also has EEPROM mapped at 0,3FFF

[T89C51AC2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 400-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# can enable boot block F800-FFFF
# has 2K EEPROM on board

[T89C51CC01]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-7FFF,F800-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer
# F800-FFFF(boot) can be disabled via SFR

[T89C51CC02]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
ROM = 0-3FFF,F800-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer
# F800-FFFF(boot) can be disabled via SFR

[T89C51IC2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable length MOVX instruction
# has 1024 bytes XRAM which can be resized, default value is 256

[T89C51RB2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM resizable from 0,256,512,768,1024
# XRAM size selected at reset is 256 bytes
# variable speed MOVX

[T89C51RC2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# XRAM resizable from 0,256,512,768,1024
# XRAM size selected at reset is 256 bytes
# variable speed MOVX

[T89C51RD2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data ptr, XRAM=0000-03FF
# XRAM resizable from 0,256,512,768,1024
# XRAM size selected at reset is 768 bytes
# has 2k EEPROM 0,7FF
# variable speed MOVX

[TDA8006]
MAKE = PHILIPS
INTRAM = 100
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has additional 1K peripheral RAM. Access is via SFRs.

[TEE502]
MAKE = TRISCEND
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# memory interface unit allows greater external access, massive external data/prog access (256K)
# this chip has many features that are not supported

[TEE505]
MAKE = TRISCEND
INTRAM = 100
XRAM = 0-3FFF
OFFRAM = 4000-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# memory interface unit allows greater external access, massive external data/prog access (256K)
# this chip has many features that are not supported

[TEE512]
MAKE = TRISCEND
INTRAM = 100
XRAM = 0-7FFF
OFFRAM = 8000-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# memory interface unit allows greater external access, massive external data/prog access (256K)
# this chip has many features that are not supported

[TEE520]
MAKE = TRISCEND
INTRAM = 100
XRAM = 0-9FFF
OFFRAM = A000-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# memory interface unit allows greater external access, massive external data/prog access (256K)
# this chip has many features that are not supported

[TEE532]
MAKE = TRISCEND
INTRAM = 100
XRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# memory interface unit allows greater external access, massive external data/prog access (256K)
# this chip has many features that are not supported

[TS80C31X2]
MAKE = ATMEL
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data ptr

[TS80C32X2]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[TS80C51RA2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[TS80C51RD2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 300-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[TS80C51U2]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[TS80C52X2]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[TS80C54X2]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[TS80C58X2]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[TS83C51RB2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[TS83C51RC2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[TS83C51RD2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 300-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[TS83C51U2]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[TS87C51RB2]
MAKE = ATMEL
INTRAM = 100 
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[TS87C51RC2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[TS87C51RD2]
MAKE = ATMEL
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 300-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[TS87C51U2]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[TS87C52X2]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[TS87C54X2]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[TS87C58X2]
MAKE = ATMEL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# dual data pointer

[TSC73M2910]
MAKE = TDK
INTRAM = 100
#XRAM = 0,FF
OFFRAM = 100-FFFF
ROM = 0-FFFF
#BANKS = 0,3
BANKADR = 8000-FFFF
BANKTYPE = T
INSTR = MCS-51
ARCH = 8051
# has on-board RAM 0-FF but is reserved

[TSC73M2910A]
MAKE = TDK
INTRAM = 100
#XRAM = 0,FF
OFFRAM = 100-FFFF
ROM = 0-FFFF
#BANKS = 0,3
BANKADR = 8000-FFFF
BANKTYPE = T
INSTR = MCS-51
ARCH = 8051
# has on-board RAM 0-FF but is reserved

[TSC73M2910L]
MAKE = TDK
INTRAM = 100
#XRAM = 0,FF
OFFRAM = 100-FFFF
ROM = 0-FFFF
#BANKS = 0,3
BANKADR = 8000-FFFF
BANKTYPE = T
INSTR = MCS-51
ARCH = 8051
# has on-board RAM 0-FF but is reserved

[TSC80C31]
MAKE = TEMIC
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[TSC80C32]
MAKE = TEMIC
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[TSC80C51]
MAKE = TEMIC
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[TSC80C52]
MAKE = TEMIC
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[TSC87C51]
MAKE = TEMIC
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[TUSB2136]
MAKE = TI
INTRAM = 100
XRAM = FD80-FEEF
OFFRAM = FF00-FF7F
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# has boot rom at 8000-97FF
# these definitions are for normal mode, not boot mode of this device
# XFRs are mapped in external data FF80-FFFF
# setup buffer and EDB are defined as OFFRAM

[TUSB3200]
MAKE = TI
INTRAM = 100
OFFRAM = F800-FF2F
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# Runtime registers mapped into external data region FF30-FFFF
# user can access USB endpoint buffers space FF80-FF2F by defining external RAM.

[TUSB3210]
MAKE = TI
INTRAM = 100
XRAM = FD80-FEEF
OFFRAM = FF00-FF7F
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# has boot rom at 8000-97FF
# these definitions are for normal mode, not boot mode of this device
# XFRs are mapped in external data FF80-FFFF
# setup buffer and EDB are defined as OFFRAM

[TUSB3410]
MAKE = TI
INTRAM = 100
XRAM = F800-FF7F
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# has boot rom at 8000-A7FF
# these definitions are for normal mode, not boot mode of this device
# XFRs are mapped in external data FF80-FFFF

[TUSB5052]
MAKE = TI
INTRAM = 100
XRAM = F800-FF7F
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# has boot rom at 8000-97FF
# these definitions are for normal mode, not boot mode of this device
# XFRs are mapped in external data FF80-FFFF

[TUSB5152]
MAKE = TI
INTRAM = 100
XRAM = F800-FF7F
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# has boot rom at 8000-97FF
# these definitions are for normal mode, not boot mode of this device
# XFRs are mapped in external data FF80-FFFF

[U51F128S02]
MAKE = WINEDGE
INTRAM = 100
XRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
BANKROM = C000-FFFFF
BANKADR = C000-FFFF
BANKTYPE = G
INSTR = NON STANDARD
ARCH = 8051
# some instructions have been replaced with new ones
# we do not support the banked internal memory scheme used on this chip.
# This chip has 4 independent banking windows, 3 can access 1 of 255 banks.
# The other window can access 1 of 7.
# This setting has enabled only the uppermost of these windows.
# Each window can be configured to point to ROM/RAM/IO, however we do not
# support this feature.
# We presently do not support banks 0,1 & 2 appearing in bank window. 

[U51F64S02]
MAKE = WINEDGE
INTRAM = 100
XRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
BANKROM = C000-FFFFF
BANKADR = C000-FFFF
BANKTYPE = G
INSTR = NON STANDARD
ARCH = 8051
# some instructions have been replaced with new ones
# we do not support the banked internal memory scheme used on this chip.
# This chip has 4 independent banking windows, 3 can access 1 of 255 banks.
# The other window can access 1 of 7.
# This setting has enabled only the uppermost of these windows.
# Each window can be configured to point to ROM/RAM/IO, however we do not
# support this feature.
# We presently do not support banks 0,1 & 2 appearing in bank window. 

[UPSD3212A]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 16K of secondary flash memory
# has 0-7FF XRAM that can be mapped into any address with PSD tool

[UPSD3212CV]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 16K of secondary flash memory
# has 0-7FF XRAM that can be mapped into any address with PSD tool

[UPSD3212C]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 16K of secondary flash memory
# has 0-7FF XRAM that can be mapped into any address with PSD tool

[UPSD3233A]
MAKE = ST
INTRAM = 100
XRAM = 0-FF
OFFRAM = 100-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has massive ammounts of program memory available.
# has a secondary flash memory of 32K.
# has an additional external RAM section (PSD 8K) not described here.
# 8K PSD RAM can be mapped anywhere in external RAM range.
# banking done with debug tool.

[UPSD3233BV]
MAKE = ST
INTRAM = 100
XRAM = FF00-FFFF
OFFRAM = 0-FEFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has massive ammounts of program memory available.
# has a secondary flash memory of 32K.
# has an additional external RAM section (PSD 8K) not described here.
# 8K PSD RAM can be mapped anywhere in external RAM range.
# banking done with debug tool.

[UPSD3233B]
MAKE = ST
INTRAM = 100
XRAM = FF00-FFFF
OFFRAM = 0-FEFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has massive ammounts of program memory available.
# has a secondary flash memory of 32K.
# has an additional external RAM section (PSD 8K) not described here.
# 8K PSD RAM can be mapped anywhere in external RAM range.
# banking done with debug tool.

[UPSD3234A]
MAKE = ST
INTRAM = 100
XRAM = FF00-FFFF
OFFRAM = 0-FEFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has massive ammounts of program memory available.
# has a secondary flash memory of 32K.
# has an additional external RAM section (PSD 8K) not described here.
# 8K PSD RAM can be mapped anywhere in external RAM range.
# banking done with debug tool.

[UPSD3234BV]
MAKE = ST
INTRAM = 100
XRAM = FF00-FFFF
OFFRAM = 0-FEFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has massive ammounts of program memory available.
# has a secondary flash memory of 32K.
# has an additional external RAM section (PSD 8K) not described here.
# 8K PSD RAM can be mapped anywhere in external RAM range.
# banking done with debug tool.

[UPSD3234B]
MAKE = ST
INTRAM = 100
XRAM = FF00-FFFF
OFFRAM = 0-FEFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has massive ammounts of program memory available.
# has a secondary flash memory of 32K.
# has an additional external RAM section (PSD 8K) not described here.
# 8K PSD RAM can be mapped anywhere in external RAM range.
# banking done with debug tool.

[UPSD3253BV]
MAKE = ST
INTRAM = 100
XRAM = FF00-FFFF
OFFRAM = 0-FEFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has 1FFFF of program memory available.
# has a secondary flash memory of 32K.
# has an additional external RAM section (PSD 8K) not described here.
# 8K PSD RAM can be mapped anywhere in external RAM range.

[UPSD3253B]
MAKE = ST
INTRAM = 100
XRAM = FF00-FFFF
OFFRAM = 0-FEFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has 1FFFF of program memory available.
# has a secondary flash memory of 32K.
# has an additional external RAM section (PSD 8K) not described here.
# 8K PSD RAM can be mapped anywhere in external RAM range.

[UPSD3254A]
MAKE = ST
INTRAM = 100
XRAM = FF00-FFFF
OFFRAM = 0-FEFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has 3FFFF of program memory available.
# has a secondary flash memory of 32K.
# has an additional external RAM section (PSD 8K) not described here.
# 8K PSD RAM can be mapped anywhere in external RAM range.

[UPSD3254BV]
MAKE = ST
INTRAM = 100
XRAM = FF00-FFFF
OFFRAM = 0-FEFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has 3FFFF of program memory available.
# has a secondary flash memory of 32K.
# has an additional external RAM section (PSD 8K) not described here.
# 8K PSD RAM can be mapped anywhere in external RAM range.

[UPSD3312DV]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has secondary flash of 16K.
# Has 2K of SRAM which can be remapped anywhere within 64K space.
# Has CSIOP memory 100h bytes.

[UPSD3312D]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has secondary flash of 16K.
# Has 2K of SRAM which can be remapped anywhere within 64K space.
# Has CSIOP memory 100h bytes.

[UPSD3333DV]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Actually has 128K of primary flash memory.
# Has secondary flash of 32K.
# Has 8K of SRAM which can be remapped anywhere within 64K space.
# Has CSIOP memory 100h bytes.

[UPSD3333D]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Actually has 128K of primary flash memory.
# Has secondary flash of 32K.
# Has 8K of SRAM which can be remapped anywhere within 64K space.
# Has CSIOP memory 100h bytes.

[UPSD3334DV]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Actually has 256K of primary flash memory.
# Has secondary flash of 32K.
# Has 8K of SRAM which can be remapped anywhere within 64K space.
# Has CSIOP memory 100h bytes.

[UPSD3334D]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Actually has 256K of primary flash memory.
# Has secondary flash of 32K.
# Has 8K of SRAM which can be remapped anywhere within 64K space.
# Has CSIOP memory 100h bytes.

[UPSD3354DV]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Actually has 256K of primary flash memory.
# Has secondary flash of 32K.
# Has 32K of SRAM which can be remapped anywhere within 64K space.
# Has CSIOP memory 100h bytes.

[UPSD3354D]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Actually has 256K of primary flash memory.
# Has secondary flash of 32K.
# Has 32K of SRAM which can be remapped anywhere within 64K space.
# Has CSIOP memory 100h bytes.

[UPSD3422EV]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has 64K of primary flash memory.
# Has 32K of secondary flash memory.
# Has 4K of SRAM which can be remapped anywhere within 64K space.

[UPSD3422E]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has 64K of primary flash memory.
# Has 32K of secondary flash memory.
# Has 4K of SRAM which can be remapped anywhere within 64K space.

[UPSD3433EV]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has 128K of primary flash memory.
# Has 32K of secondary flash memory.
# Has 8K of SRAM which can be remapped anywhere within 64K space.

[UPSD3433E]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has 128K of primary flash memory.
# Has 32K of secondary flash memory.
# Has 8K of SRAM which can be remapped anywhere within 64K space.

[UPSD3434EV]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has 256K of primary flash memory.
# Has 32K of secondary flash memory.
# Has 8K of SRAM which can be remapped anywhere within 64K space.

[UPSD3434E]
MAKE = ST
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has 128K of primary flash memory.
# Has 32K of secondary flash memory.
# Has 8K of SRAM which can be remapped anywhere within 64K space.

[USB97C100]
MAKE = SMSC
INTRAM = 80
XRAM = 7000-7EFF
OFFRAM = 4000-6FFF,8000-FFFF
ROM = 0-BFFF
#BANKS = 3,63
BANKADR = 4000-7FFF
BANKTYPE = U
INSTR = MCS-51
ARCH = 8051
# external data memory has mapped into address range.
# user must enable ISA/MMU address ranges with external RAM option if needed.
# Lower flash banks 0,1,2 only accessable in user code.
# upper MEMBANK window (C000-FFFF) mirrors (4000-7FFF), not supported.
# external runtime registers mapped into external addresses 7F00-7FFF.
# External data memory 8000-FFFF accesses program flash areas.
# user can enable this data area at own risk by specifying external RAM range.

[USB97C102]
MAKE = SMSC
INTRAM = 80
XRAM = 7000-7EFF
OFFRAM = 4000-6FFF,8000-FFFF
ROM = 0-BFFF
BANKROM = 8000-FFFFF
BANKADR = 8000-BFFF
BANKTYPE = V
INSTR = MCS-51
ARCH = 8051
# external data memory has mapped into address range.
# user must enable ISA/MMU address ranges with external RAM option if needed.
# Lower flash banks 0,1,2 only accessable in user code.
# upper MEMBANK window (C000-FFFF) mirrors (4000-7FFF), not supported.
# external runtime registers mapped into external addresses 7F00-7FFF.
# this chip has 2 ROM bank windows. we support only the MEMBANK2 window.
# External data memory 8000-FFFF accesses program flash areas.
# user can enable this data area at own risk by specifying external RAM range.

[USB97C201]
MAKE = SMSC
INTRAM = 100
XRAM = 400-6FF
OFFRAM = 700-30EF,30F4-31EF,30F8-33F5,33F7-3EFF,3F30-FFFF
OFFROM = 0-3FF,700-FFFF
INSTR = MCS-51
ARCH = 8051
# external data memory has test registers etc throughout its range.
# Runtime SFRs are mapped into external data 0-1FF.

[UT69RH051]
MAKE = AEROFLEX
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[V87C54]
MAKE = VERSACHIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[V87C58]
MAKE = VERSACHIPS
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[VERSA1B]
MAKE = GOAL
INTRAM = 100
XRAM = 0-3FF
#XRAM = 806,994
#XRAM = A11,FFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has a block of flash memory mapped into RAM addresses 800-FFF.
# Some small address ranges are reserved in the flash block.
# has a multply accumulator module for accelerated arithmetic ops.

[VERSA1]
MAKE = GOAL
INTRAM = 100
XRAM = 0-3FF
#XRAM = 806,994
#XRAM = A11,FFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has a block of flash memory mapped into RAM addresses 800-FFF.
# Some small address ranges are reserved in the flash block.
# has a multply accumulator module for accelerated arithmetic ops.

[VERSAMIX]
MAKE = GOAL
INTRAM = 100
XRAM = 0-3FF
#XRAM = 806,994
#XRAM = A11,FFF
ROM = 0-DFFF
INSTR = MCS-51
ARCH = 8051
# Has a block of flash memory mapped into RAM addresses 800-FFF.
# Some small address ranges are reserved in the flash block.
# has a multply accumulator module for accelerated arithmetic ops.

[VRS1000]
MAKE = GOAL
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 300-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# program address F000-FFFF is for ISP, configurable code/ISP partition
# device can go into mode where XRAM is directly accessed in 16 banks of 3Fh.

[VRS1100]
MAKE = GOAL
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has MPAGE register which can be used to modify the behaviour of MOVX @Ri
# DBANK register can change remap ranges of RAM into lower internal 40-7F.

[VRS540]
MAKE = GOAL
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 1000-FFFF
INSTR = MCS-51
ARCH = 8051

[VRS550]
MAKE = GOAL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 2000-FFFF
INSTR = MCS-51
ARCH = 8051

[VRS560]
MAKE = GOAL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 4000-FFFF
INSTR = MCS-51
ARCH = 8051

[VRS570]
MAKE = GOAL
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 300-FFFF
ROM = 0-7FFF
OFFROM = 8000-FFFF
INSTR = MCS-51
ARCH = 8051
# expanded RAM area can be disabled via SFR

[VRS580]
MAKE = GOAL
INTRAM = 100
XRAM = 0-2FF
OFFRAM = 300-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# expanded RAM area can be disabled via SFR

[VRS700L]
MAKE = GOAL
INTRAM = 100
XRAM = 0-EFF
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# expanded RAM area can be disabled via SFR

[VRS700]
MAKE = GOAL
INTRAM = 100
XRAM = 0-EFF
OFFRAM = F00-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# expanded RAM area can be disabled via SFR

[VRS900]
MAKE = GOAL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 2000-FFFF
INSTR = MCS-51
ARCH = 8051

[W77C32]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# 0,3FF SRAM available via SFR, but disabled by default.
# Do not support DEC DPTR (A5)

[W77C58]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# 0,3FF SRAM available via SFR, but disabled by default.
# Do not support DEC DPTR (A5)

[W77E468]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# 0,3FF SRAM available via SFR, but disabled by default.
# Do not support DEC DPTR (A5)

[W77E516]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 4K boot memory

[W77E532]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
#BANKADR = 8000,FFFF
#BANKTYPE = W
INSTR = MCS-51
ARCH = 8051
# chip can bank entire 64K program space.
# Do not support DEC DPTR (A5)

[W77E58]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# 0,3FF SRAM available via SFR, but disabled by default.
# Do not support DEC DPTR (A5)

[W77IC32]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# 0,3FF SRAM available via SFR, but disabled by default.
# Do not support DEC DPTR (A5)

[W77IE58]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# 0,3FF SRAM available via SFR, but disabled by default.
# Do not support DEC DPTR (A5)

[W77L32]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Do not support DEC DPTR (A5)

[W77LE58]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# also has 4k loader ROM
# 0,FF AUXRAM available via SFR, but disabled by default.
# Do not support DEC DPTR (A5)

[W78C32]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[W78C33]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[W78C374]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-FF
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# have additional SFRS mapped into 80-BF external data space

[W78C378]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# have additional SFRS mapped into 80-BF external data space

[W78C438C]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# we do not support the paged data memory features of this chip

[W78C51D]
MAKE = WINBOND
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR =  MCS-51
ARCH = 8051

[W78C52D]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[W78C52]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[W78C54]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[W78C58]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[W78C801]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[W78E354]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-FF
ROM = 0-3FFF
OFFROM = 0-0FFF
INSTR = MCS-51
ARCH = 8051

[W78E365]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# MOVC inhibit not supported

[W78E378]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# have additional SFRS mapped into 80-BF external data space

[W78E516B]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 4K of loader ROM + security register
# 0,FF AUXRAM available via SFR, but disabled by default.
# MOVC inhibit not supported

[W78E51B]
MAKE = WINBOND
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# MOVC inhibit not supported

[W78E52B]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# MOVC inhibit not supported

[W78E54B]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# MOVC inhibit not supported

[W78E58B]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFF
INSTR = MCS-51
ARCH = 8051
# MOVC inhibit not supported

[W78E62]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[W78E65]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[W78E858]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-1FF
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 4K boot memory
# MOVC lock not supported

[W78IE52]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# MOVC inhibit not supported

[W78IE54]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# MOVC inhibit not supported

[W78L32]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-3FFF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[W78L51]
MAKE = WINBOND
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[W78L52]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[W78L54]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[W78L801]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[W78LE516]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 4K of loader ROM + security register
# 0,FF AUXRAM available via SFR, but disabled by default.
# MOVC inhibit not supported

[W78LE51]
MAKE = WINBOND
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# MOVC inhibit not supported

[W78LE52]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# MOVC inhibit not supported

[W78LE54]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# MOVC inhibit not supported

[W78LE58]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 4K of loader ROM + security register
# 0,FF AUXRAM available via SFR, but disabled by default.
# MOVC inhibit not supported

[W78LE812]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# MOVC inhibit not supported

[W81E381AD]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
ROM = 0-4FFF
# MOVC lock not supported

[W81E381D]
MAKE = WINBOND
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
ROM = 0-4FFF
# MOVC lock not supported

[W925C240]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-1FFF
ROM = 0-FFFF
INSTR = MCS-51 plus DEC DPTR (A5)
ARCH = 8051
# Serial port is slightly different from traditional 8051 serial port
# this chip can bank program memory, but banks are 64k in size (not supported)
# total program memory is 3FFFFh
# has additional instruction: DEC DPTR (A5)

[W925C625]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-FFF,2000-20FE
ROM = 0-FFFF
INSTR = MCS-51 plus DEC DPTR (A5)
ARCH = 8051
# XRAM 2000-20FE is for LCD
# Serial port is slightly different from traditional 8051 serial port
# has additional instruction: DEC DPTR (A5)

[W925E240]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-1FFF
ROM = 0-FFFF
INSTR = MCS-51 plus DEC DPTR (A5)
ARCH = 8051
# Serial port is slightly different from traditional 8051 serial port
# this chip can bank program memory, but banks are 64k in size (not supported)
# total program memory is 3FFFFh
# has additional instruction: DEC DPTR (A5)

[W925E625]
MAKE = WINBOND
INTRAM = 100
XRAM = 0-FFF,2000-20FE
ROM = 0-FFFF
INSTR = MCS-51 plus DEC DPTR (A5)
ARCH = 8051
# XRAM 2000-20FE is for LCD
# Serial port is slightly different from traditional 8051 serial port
# has additional instruction: DEC DPTR (A5)

[ZE502]
MAKE = ZYLOGIC
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# custom define memory spaces

[ZE505]
MAKE = ZYLOGIC
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# custom define memory spaces

[ZE512]
MAKE = ZYLOGIC
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# custom define memory spaces

[ZE520]
MAKE = ZYLOGIC
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# custom define memory spaces

[ZE532]
MAKE = ZYLOGIC
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# custom define memory spaces
