{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":403618268,"defaultBranch":"main","name":"Basic-combinational-logic-VHDL","ownerLogin":"saibhargav1508","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2021-09-06T12:41:16.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/20701792?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1630932358.300409","currentOid":""},"activityList":{"items":[],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"startCursor":null,"endCursor":null}},"title":"Activity · saibhargav1508/Basic-combinational-logic-VHDL"}