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axi_cdc fpga implementation very inefficient #294
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Hi sir, I've been reviewing the axi_cdc, but can't find the definitions for cdc_fifo_gray_src and cdc_fifo_gray_dst modules. |
Hi @skokvermon, |
Hi
axi_cdc uses fifos that don't infer dual SRAM. Fifo is implemented using registers, and it is very slow.
In my design, I had to lower fifo depth to 8 words in order to be able to run at 100mhz.
fifo_v3 also don't infer SRAM, which is very problematic.
I could succesfully use single and dual clock fifos from optimsoc which can infer xilinx SRAM (and probably altera too).
I think it would be nice to use such fifos for axi_cdc
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