[Question] AXI Ordering

[Yuan-Mao]

Hi I have a question about the axi_lite_from_mem module:
https://github.com/pulp-platform/axi/blob/master/src/axi_lite_from_mem.sv#L176

Looks like the module uses a FIFO to track the read/write order of all incoming transactions and asserts bready and rready in that same order. However, if I understand correctly, the AXI protocol does not require that read and write transactions to be completed in order. Therefore could the module stall if a downstream AXIL slave reorders its responses (for example, reorder r->w to w->r)?

Thanks!