Construct truth tables for the following logic gates:
- NOT
- AND
- OR
- XOR
- NAND
- NOR
| Name | Truth Table | Shape | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| NOT |
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| AND |
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| OR |
|
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| XOR |
|
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| NAND |
|
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| NOR |
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A flip-flop is a type of circuit which contains two states is often used to store state information. It can only store one bit.
An S-R Flip Flop is a flip flop which has a set and reset function.
Truth Table
Anytime a flip-flop is set, Q goes high.
Anytime a flip-flop is reset, Q goes low.
| S | R | Q | !Q |
|---|---|---|---|
| 0 | 0 | Q | !Q |
| 1 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | 1 | X | X |
The 1,1 input has undetermined output.
Be familiar with the use of the edge-triggered D-type flip-flop as a memory unit.
A D-type flip flop uses an enabler to be able to easily manage the stored state. If the enabler is low then nothing will change in the state, however if the enable is high then the state man be modified.
| Enabler | X | Q |
|---|---|---|
| 0 | 0 | Q |
| 0 | 1 | Q |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
In a positive edge-triggered D-type flip flop, when the clock goes high then Q can change however if D changes when the clock is already high, then the value doesn't change.
Symbol for positive edge trigger
In a negative edge-triggered D-type flip-flop, when the clock is going low then Q can change however at any other time Q cannot change.
Symbol for negative edge trigger
A D-type flip flop can be used in:
- counters
- shift registers
- other single memory units
Recognise and trace the logic of the circuits of a half-adder and a full-adder.
Construct the circuit for a half-adder.
A half adder can take in two bits and output the sum of them including the carry bit.
Truth Table for half-adder
| A | B | C | S |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 |
The full adder is an extension of the half adder as it allows for an input carry bit to be used.
Truth Table for full-adder
| A | B | C in | C out | S |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 |
Additional Information
Knowledge of internal operation of this flip-flop is not required.