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1. Verification_ULA_UVM_methodology Verification_ULA_UVM_methodology Public

   Verification of an Arithmetic Logic Unit (ULA/ALU) capable of performing 7 operations

   SystemVerilog

2. AES128_RTLsynthesis AES128_RTLsynthesis Public

   logical and physical synthesis of a 128-bit encryption core, AES128, starting from an RTL available on the OpenCores website and synthesis tools from the company Cadence

   Verilog 1

3. Drift_test_LoRa Drift_test_LoRa Public

   Automated drift test for LoRa device using Rohde and Schwarz spectrum analyser

   Python

4. Test_result_analysis Test_result_analysis Public

   Using a python script to analyse the results of a characterization test of generic device

   Python

5. DAQ_VIs DAQ_VIs Public

   Usefull VIs to use in LabView to interact with data from DAQ

6. LoRa_Wave_Generator_LabView_RS LoRa_Wave_Generator_LabView_RS Public

   Generation of a LoRa Wave with R&S wave generator and LabView