diff --git a/testbench/cocotb/Makefile b/testbench/cocotb/Makefile
index 216e6a5..7ec5657 100644
--- a/testbench/cocotb/Makefile
+++ b/testbench/cocotb/Makefile
@@ -19,12 +19,14 @@ include $(shell cocotb-config --makefiles)/Makefile.sim
 		test_mux2to1	\
 		test_mux4to1 	\
 		test_DFF_reg	\
+		test_addSubtractor	\
 		cleanup
 
 all:	test_microprocessor  \
 		test_mux2to1 	\
 		test_mux4to1	\
 		test_DFF_reg	\
+		test_addSubtractor	\
 		cleanup		
 
 # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
@@ -86,6 +88,17 @@ test_DFF_reg:
 	@echo "VERILOG_SOURCES=$(VERILOG_SOURCES)"
 	$(MAKE) sim TOPLEVEL=$(TOPLEVEL) MODULE=$(MODULE) VERILOG_SOURCES="$(VERILOG_SOURCES)"
 
+test_addSubtractor:
+	$(MAKE) cleanup
+	$(info Running test_addSubtractor...)
+	$(eval TOPLEVEL := addSubstractor)
+	$(eval MODULE := test_addSubtractor)
+
+	@echo "TOPLEVEL=$(TOPLEVEL)"
+	@echo "MODULE=$(MODULE)"
+	@echo "VERILOG_SOURCES=$(VERILOG_SOURCES)"
+	$(MAKE) sim TOPLEVEL=$(TOPLEVEL) MODULE=$(MODULE) VERILOG_SOURCES="$(VERILOG_SOURCES)"
+
 cleanup:
 	$(info Cleaning up generated files...)
 	$(RM) -vf *.vvp sim_build/* results.xml
diff --git a/testbench/cocotb/test_addSubtractor.py b/testbench/cocotb/test_addSubtractor.py
new file mode 100644
index 0000000..b6211ca
--- /dev/null
+++ b/testbench/cocotb/test_addSubtractor.py
@@ -0,0 +1,67 @@
+import cocotb
+from cocotb.triggers import RisingEdge, Timer
+
+
+async def initialize(dut):
+    dut.A.value  = 0
+    dut.B.value  = 0
+    dut.sub.value  = 0
+    await Timer(1, units="ns")
+
+
+@cocotb.test()
+async def test_addSubtractor_add(dut):
+    await initialize(dut)  # Call the initialization function
+    
+    dut._log.info("Initialization DONE!")
+    await Timer(5, units="ns")  # wait a bit
+
+    dut.sub.value = 0
+    dut._log.info(f"Signal sub is set to {dut.sub.value}")
+
+    dut._log.info(f"Test:   A(0) + B(1)")
+    dut.A.value = 0
+    dut.B.value = 1
+    await Timer(1, units="ns")
+    assert dut.out.value == 1, f"Expected 1 but got {dut.out.value}"
+    assert dut.A.value == 0, f"Expected 0 but got {dut.A.value}"
+    assert dut.B.value == 1, f"Expected 1 but got {dut.B.value}"
+    assert dut.sub.value == 0, f"Expected 0 but got {dut.sub.value}"
+
+    dut._log.info(f"Test:   A(1) + B(1)")
+    dut.A.value = 1
+    dut.B.value = 1
+    await Timer(1, units="ns")
+    assert dut.out.value == 2, f"Expected 1 but got {dut.out.value}"
+    assert dut.A.value == 1, f"Expected 0 but got {dut.A.value}"
+    assert dut.B.value == 1, f"Expected 1 but got {dut.B.value}"
+    assert dut.sub.value == 0, f"Expected 0 but got {dut.sub.value}"
+
+
+@cocotb.test()
+async def test_addSubtractor_sub(dut):
+    await initialize(dut)  # Call the initialization function
+    
+    dut._log.info("Initialization DONE!")
+    await Timer(5, units="ns")  # wait a bit
+
+    dut.sub.value = 1
+    dut._log.info(f"Signal sub is set to {dut.sub.value}")
+
+    dut._log.info(f"Test:   A(1) - B(0)")
+    dut.A.value = 1
+    dut.B.value = 0
+    await Timer(1, units="ns")
+    assert dut.out.value == 1, f"Expected 1 but got {dut.out.value}"
+    assert dut.A.value == 1, f"Expected 0 but got {dut.A.value}"
+    assert dut.B.value == 0, f"Expected 1 but got {dut.B.value}"
+    assert dut.sub.value == 1, f"Expected 0 but got {dut.sub.value}"
+
+    dut._log.info(f"Test:   A(1) - B(1)")
+    dut.A.value = 1
+    dut.B.value = 1
+    await Timer(1, units="ns")
+    assert dut.out.value == 0, f"Expected 1 but got {dut.out.value}"
+    assert dut.A.value == 1, f"Expected 0 but got {dut.A.value}"
+    assert dut.B.value == 1, f"Expected 1 but got {dut.B.value}"
+    assert dut.sub.value == 1, f"Expected 0 but got {dut.sub.value}"
\ No newline at end of file