VHDL clone of J1 forth CPU
This project has been developed with quartus so the RAM section will need modifying if you want to use with another FPGA vendor.
There is a demo binary hex file which can be loaded into the ram, and displays a count on a 4 digit seven segment display.
See https://excamera.com/sphinx/fpga-j1.html for more info about the J1 forth cpu.