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J1VH.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
# Date created = 19:52:24 May 09, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# J1DL_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C6
set_global_assignment -name TOP_LEVEL_ENTITY j1vh_demo
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:52:24 MAY 09, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb_j1vh -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_NAME tb_j1 -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_j1
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_j1 -section_id tb_j1
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA"
set_global_assignment -name EDA_TEST_BENCH_NAME tb_j1vh -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_j1vh
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_j1vh -section_id tb_j1vh
set_global_assignment -name EDA_TEST_BENCH_FILE tb_j1.v -section_id tb_j1 -hdl_version Verilog_2001
set_global_assignment -name EDA_TEST_BENCH_FILE tb_j1vh.vhd -section_id tb_j1vh
set_global_assignment -name VHDL_FILE j1vh_demo.vhd
set_global_assignment -name VHDL_FILE seven_seg_hex.vhd
set_global_assignment -name VHDL_FILE tb_j1vh.vhd
set_global_assignment -name VHDL_FILE j1vh.vhd
set_global_assignment -name VERILOG_FILE tb_j1.v
set_global_assignment -name VERILOG_FILE j1.v
set_global_assignment -name QIP_FILE Ram.qip
set_global_assignment -name QIP_FILE dual_port_ram.qip
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_2 -to segments[6]
set_location_assignment PIN_138 -to segments[5]
set_location_assignment PIN_142 -to segments[4]
set_location_assignment PIN_141 -to segments[3]
set_location_assignment PIN_1 -to segments[2]
set_location_assignment PIN_144 -to segments[1]
set_location_assignment PIN_143 -to segments[0]
set_location_assignment PIN_133 -to cathodes[3]
set_location_assignment PIN_136 -to cathodes[2]
set_location_assignment PIN_135 -to cathodes[1]
set_location_assignment PIN_137 -to cathodes[0]
set_location_assignment PIN_24 -to clk
set_location_assignment PIN_89 -to nrst
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top