From b55230fedbe86371d1108714ffa49c2c6b3613ce Mon Sep 17 00:00:00 2001
From: Xeonacid <h.dwwwwww@gmail.com>
Date: Wed, 20 Nov 2024 06:52:42 -0500
Subject: [PATCH] upgpatch: spike 1.1.0-5

---
 spike/riscv64.patch | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/spike/riscv64.patch b/spike/riscv64.patch
index 3dff5c77a..aa170ed7f 100644
--- a/spike/riscv64.patch
+++ b/spike/riscv64.patch
@@ -1,19 +1,16 @@
 diff --git PKGBUILD PKGBUILD
-index 30c0623..adb63dd 100644
+index 1bd6efa..c65320b 100644
 --- PKGBUILD
 +++ PKGBUILD
-@@ -18,6 +18,14 @@ makedepends=(git)
- source=("git+https://github.com/riscv/riscv-isa-sim#commit=530af85d83781a3dae31a4ace84a573ec255fefa") # tag: v1.1.0
- b2sums=(SKIP)
+@@ -20,6 +20,11 @@
  
-+prepare(){
-+  cd riscv-isa-sim
+ prepare() {
+   sed -i '/#include <cstring>/a #include <cstdint>' riscv-isa-sim/fesvr/device.h
 +
++  cd riscv-isa-sim
 +  # Commits from https://github.com/riscv-software-src/riscv-isa-sim/pull/966
 +  git cherry-pick -n e52327deeefb29908a822a9eb2f6fc5c87e968af
 +  git cherry-pick -n dba7efaf9e2e8d5251820c8555a184f715bb4d46
-+}
-+
+ }
+ 
  build() {
-   cd riscv-isa-sim
-   ./configure --prefix=/usr