RISE RP005 QEMU weekly report 2024-10-30

Version 4 of the patches is upstream.

Work completed since last report

Upstream fixes for the latest feedback.
- Pushed a new version of the patches (v4).
- V5 might be needed to find an alternative way to generate atomic memory operations.
- No issues found with patch 1 of the patch set (small vectors).
Start optimization for whole register load/store operations through tcg op generation.
- nothing to report yet.
- we're looking into adding resources to speed up the work.
Investigate the SIGILL QEMU error in the SiFive library functions
- the error might be due a bad combination of LMUL and VLEN with some instructions (thanks Nathan for suggesting).
- Jeremy has been improving the scripts and aims at having the issue resolved by the end of the month.
Actions:
- Paolo to update the slides for the RISC-V Summit.
  - COMPLETE.

Work planned for the coming week

WP2
- Address any new comments on patch 2 (it might not need new implementations, just a better description).
- Continue the optimization work for whole register load/store operations through tcg op generation.
- Ultimate the scripts for the SiFive tests.

Planned absences

Paolo Savini will be on vacation 8 November and 13-18 November

Project Invoicing

MS0 and MS1 paid
Pending agreed deliverables and RISE approval:
MS2 Oct-31, 2024
MS3 Dec-16, 2024