From 30f4d828db3d6a6f06645b43e904109c84ea3f34 Mon Sep 17 00:00:00 2001 From: mo-hosni Date: Mon, 18 Mar 2024 12:40:40 +0200 Subject: [PATCH] remove `sparecell` std cell macro because it causes DRCs --- verilog/rtl/gpio_control_block.v | 18 +++++++++--------- verilog/rtl/gpio_control_block_mgmt.v | 18 +++++++++--------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v index e1b6f660..ca0cf235 100644 --- a/verilog/rtl/gpio_control_block.v +++ b/verilog/rtl/gpio_control_block.v @@ -250,15 +250,15 @@ module gpio_control_block #( /* going to the user project. */ assign user_gpio_in = pad_gpio_in & gpio_logic1; - (* keep *) - sky130_fd_sc_hd__macro_sparecell spare_cell ( -`ifdef USE_POWER_PINS - .VPWR(vccd), - .VGND(vssd), - .VPB(vccd), - .VNB(vssd) -`endif - ); +// (* keep *) +// sky130_fd_sc_hd__macro_sparecell spare_cell ( +// `ifdef USE_POWER_PINS +// .VPWR(vccd), +// .VGND(vssd), +// .VPB(vccd), +// .VNB(vssd) +// `endif +// ); sky130_fd_sc_hd__conb_1 const_source ( `ifdef USE_POWER_PINS diff --git a/verilog/rtl/gpio_control_block_mgmt.v b/verilog/rtl/gpio_control_block_mgmt.v index 5e710dd9..82fd398c 100644 --- a/verilog/rtl/gpio_control_block_mgmt.v +++ b/verilog/rtl/gpio_control_block_mgmt.v @@ -257,15 +257,15 @@ module gpio_control_block_mgmt #( /* going to the user project. */ assign user_gpio_in = pad_gpio_in & gpio_logic1; - (* keep *) - sky130_fd_sc_hd__macro_sparecell spare_cell ( -`ifdef USE_POWER_PINS - .VPWR(vccd), - .VGND(vssd), - .VPB(vccd), - .VNB(vssd) -`endif - ); +// (* keep *) +// sky130_fd_sc_hd__macro_sparecell spare_cell ( +// `ifdef USE_POWER_PINS +// .VPWR(vccd), +// .VGND(vssd), +// .VPB(vccd), +// .VNB(vssd) +// `endif +// ); // buffering const one and zero outputs wire one_unbuf;