diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index e1b6f660..ca0cf235 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -250,15 +250,15 @@ module gpio_control_block #(
     /* going to the user project.					*/
     assign user_gpio_in = pad_gpio_in & gpio_logic1;
 
-    (* keep *)
-    sky130_fd_sc_hd__macro_sparecell spare_cell (
-`ifdef USE_POWER_PINS
-            .VPWR(vccd),
-            .VGND(vssd),
-            .VPB(vccd),
-            .VNB(vssd)
-`endif
-    );
+//     (* keep *)
+//     sky130_fd_sc_hd__macro_sparecell spare_cell (
+// `ifdef USE_POWER_PINS
+//             .VPWR(vccd),
+//             .VGND(vssd),
+//             .VPB(vccd),
+//             .VNB(vssd)
+// `endif
+//     );
 
     sky130_fd_sc_hd__conb_1 const_source (
 `ifdef USE_POWER_PINS
diff --git a/verilog/rtl/gpio_control_block_mgmt.v b/verilog/rtl/gpio_control_block_mgmt.v
index 5e710dd9..82fd398c 100644
--- a/verilog/rtl/gpio_control_block_mgmt.v
+++ b/verilog/rtl/gpio_control_block_mgmt.v
@@ -257,15 +257,15 @@ module gpio_control_block_mgmt #(
     /* going to the user project.					*/
     assign user_gpio_in = pad_gpio_in & gpio_logic1;
 
-    (* keep *)
-    sky130_fd_sc_hd__macro_sparecell spare_cell (
-`ifdef USE_POWER_PINS
-            .VPWR(vccd),
-            .VGND(vssd),
-            .VPB(vccd),
-            .VNB(vssd)
-`endif
-    );
+//     (* keep *)
+//     sky130_fd_sc_hd__macro_sparecell spare_cell (
+// `ifdef USE_POWER_PINS
+//             .VPWR(vccd),
+//             .VGND(vssd),
+//             .VPB(vccd),
+//             .VNB(vssd)
+// `endif
+//     );
 
     // buffering const one and zero outputs
     wire	one_unbuf;