diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d6cb840b7050..97bb03f85d72 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -229,5 +229,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-ayn-odin2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8550-ayn-odin2.dts b/arch/arm64/boot/dts/qcom/sm8550-ayn-odin2.dts new file mode 100644 index 000000000000..2339020a7926 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-ayn-odin2.dts @@ -0,0 +1,1202 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Xilin Wu + */ + +/dts-v1/; + +#include +#include +#include "sm8550.dtsi" +// #include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +// #include "pmr735d_a.dtsi" +// #include "pmr735d_b.dtsi" + +/ { + model = "AYN Odin 2"; + compatible = "ayn,odin2", "qcom,sm8550"; + chassis-type = "handset"; + + aliases { + serial0 = &uart7; + serial1 = &uart14; + }; + + // backlight: backlight { + // compatible = "pwm-backlight"; + // pwms = <&pwm0 0 1000000>; + // // power-supply = <&bl_pp5000>; + // enable-gpios = <&pio 176 0>; + // brightness-levels = <0 1023>; + // num-interpolated-steps = <1023>; + // default-brightness-level = <576>; + // status = "okay"; + // }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + // stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + hpd-gpios = <&tlmm 9 GPIO_ACTIVE_HIGH>; + // ddc-i2c-bus = <&i2c_hub_0>; + + port { + hdmi_con: endpoint { + remote-endpoint = <<8912_out>; + }; + }; + }; + + pmic-glink { + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_con0_hs: endpoint { + remote-endpoint = <&usb_1_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&usb0_sbu_mux>; + }; + }; + }; + }; + }; + + reserved-memory { + cont_splash_mem: cont-splash@b8000000 { + reg = <0x0 0xb8000000 0x0 0x2b00000>; + no-map; + }; + }; + + fan_pwr: fan-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "fan_pwr"; + + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + gpio = <&tlmm 109 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <255>; + #cooling-cells = <2>; + fan-supply = <&fan_pwr>; + pwms = <&pm8550_pwm 3 50000>; + + pinctrl-names = "default"; + pinctrl-0 = <&pwm_out_default>; + }; + + hdmi_pwr: hdmi-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "hdmi_pwr"; + + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + gpio = <&tlmm 10 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + + usb0-sbu-mux { + compatible = "gpio-sbu-mux"; + + enable-gpios = <&tlmm 140 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 141 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb0_sbu_default>; + + mode-switch; + orientation-switch; + + port { + usb0_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + wlan_regulator: wlan-regulator { + compatible = "regulator-wlan"; + regulator-name = "wlan"; + + enable-gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; + + supply-count = <6>; + + vin0-supply = <&vreg_l15b_1p8>; // vdd-wlan-io + vin1-supply = <&vreg_s5g_0p85>; // vdd-wlan + vin2-supply = <&vreg_s2g_0p85>; // vdd-wlan-aon + vin3-supply = <&vreg_s4e_0p95>; // vdd-wlan-dig + vin4-supply = <&vreg_s6g_1p86>; // vdd-wlan-rfa1 + vin5-supply = <&vreg_s4g_1p25>; // vdd-wlan-rfa2 + }; + +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s4g_1p25>; + vdd-l12-supply = <&vreg_s6g_1p86>; + vdd-l15-supply = <&vreg_s6g_1p86>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + // vreg_l1b_1p8: ldo1 { + // regulator-name = "vreg_l1b_1p8"; + // regulator-min-microvolt = <1800000>; + // regulator-max-microvolt = <1800000>; + // regulator-initial-mode = ; + // }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + // vreg_l6b_1p8: ldo6 { + // regulator-name = "vreg_l6b_1p8"; + // regulator-min-microvolt = <1800000>; + // regulator-max-microvolt = <3008000>; + // regulator-initial-mode = ; + // }; + + // vreg_l7b_1p8: ldo7 { + // regulator-name = "vreg_l7b_1p8"; + // regulator-min-microvolt = <1800000>; + // regulator-max-microvolt = <3008000>; + // regulator-initial-mode = ; + // }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + // vreg_l11b_1p2: ldo11 { + // regulator-name = "vreg_l11b_1p2"; + // regulator-min-microvolt = <1200000>; + // regulator-max-microvolt = <1504000>; + // regulator-initial-mode = ; + // }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + // vreg_l13b_3p0: ldo13 { + // regulator-name = "vreg_l13b_3p0"; + // regulator-min-microvolt = <3000000>; + // regulator-max-microvolt = <3000000>; + // regulator-initial-mode = ; + // }; + + // vreg_l14b_3p2: ldo14 { + // regulator-name = "vreg_l14b_3p2"; + // regulator-min-microvolt = <3200000>; + // regulator-max-microvolt = <3200000>; + // regulator-initial-mode = ; + // }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + // vreg_l16b_2p8: ldo16 { + // regulator-name = "vreg_l16b_2p8"; + // regulator-min-microvolt = <2800000>; + // regulator-max-microvolt = <2800000>; + // regulator-initial-mode = ; + // }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + // vreg_l3c_0p9: ldo3 { + // regulator-name = "vreg_l3c_0p9"; + // regulator-min-microvolt = <880000>; + // regulator-max-microvolt = <912000>; + // regulator-initial-mode = ; + // }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + /* ldo2 supplies SM8550 VDD_LPI_MX */ + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s4e_0p95: smps4 { + regulator-name = "vreg_s4e_0p95"; + // regulator-min-microvolt = <904000>; + // regulator-max-microvolt = <984000>; + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <952000>; + regulator-initial-mode = ; + }; + + vreg_s5e_1p08: smps5 { + regulator-name = "vreg_s5e_1p08"; + // regulator-min-microvolt = <1010000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name = "vreg_l1e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + // vreg_l2e_0p9: ldo2 { + // regulator-name = "vreg_l2e_0p9"; + // regulator-min-microvolt = <904000>; + // regulator-max-microvolt = <970000>; + // regulator-initial-mode = ; + // }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4f_0p5: smps4 { + regulator-name = "vreg_s4f_0p5"; + // regulator-min-microvolt = <300000>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = ; + }; + + // vreg_l1f_0p9: ldo1 { + // regulator-name = "vreg_l1f_0p9"; + // regulator-min-microvolt = <912000>; + // regulator-max-microvolt = <912000>; + // regulator-initial-mode = ; + // }; + + // vreg_l2f_0p88: ldo2 { + // regulator-name = "vreg_l2f_0p88"; + // regulator-min-microvolt = <880000>; + // regulator-max-microvolt = <912000>; + // regulator-initial-mode = ; + // }; + + vreg_l3f_0p88: ldo3 { + regulator-name = "vreg_l3f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4g_1p25>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + // vreg_s1g_1p25: smps1 { + // regulator-name = "vreg_s1g_1p25"; + // regulator-min-microvolt = <1200000>; + // regulator-max-microvolt = <1300000>; + // regulator-initial-mode = ; + // }; + + vreg_s2g_0p85: smps2 { + regulator-name = "vreg_s2g_0p85"; + // regulator-min-microvolt = <800000>; + // regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <980000>; + regulator-max-microvolt = <980000>; + regulator-initial-mode = ; + }; + + // vreg_s3g_0p8: smps3 { + // regulator-name = "vreg_s3g_0p8"; + // regulator-min-microvolt = <300000>; + // regulator-max-microvolt = <1004000>; + // regulator-initial-mode = ; + // }; + + vreg_s4g_1p25: smps4 { + regulator-name = "vreg_s4g_1p25"; + // regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_s5g_0p85: smps5 { + regulator-name = "vreg_s5g_0p85"; + // regulator-min-microvolt = <500000>; + // regulator-max-microvolt = <1004000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vreg_s6g_1p86: smps6 { + regulator-name = "vreg_s6g_1p86"; + // regulator-min-microvolt = <1800000>; + // regulator-max-microvolt = <2000000>; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + // regulator-min-microvolt = <1144000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8550/ayn/odin2/a740_zap.mbn"; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts-extended = <&tlmm 25 0x2008>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&ts_int_default &ts_reset_default>; + pinctrl-1 = <&ts_int_sleep &ts_reset_sleep>; + + vdd-supply = <&vreg_l2b_3p0>; + vio-supply = <&vreg_l12b_1p8>; + + syna,startup-delay-ms = <200>; + syna,reset-delay-ms = <200>; + + rmi4-f01@1 { + syna,nosleep-mode = <0x1>; + reg = <0x1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,rezero-wait-ms = <200>; + syna,clip-x-low = <0>; + syna,clip-y-low = <0>; + syna,clip-x-high = <1080>; + syna,clip-y-high = <1920>; + syna,sensor-type = <1>; + touchscreen-inverted-x; + // touchscreen-x-mm = <75>; + // touchscreen-y-mm = <132>; + + touchscreen-x-mm = <300>; + touchscreen-y-mm = <528>; + }; + }; +}; + +&i2c_master_hub_0 { + status = "okay"; +}; + +&i2c_hub_0 { + clock-frequency = <100000>; + status = "okay"; + + /* Not working yet, DDC bus unknown */ + hdmi-bridge@48 { + compatible = "lontium,lt8912b"; + reg = <0x48> ; + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_out_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + lt8912_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c_hub_2 { + status = "okay"; + + /* Does this exist? */ + + // typec-retimer@1c { + // compatible = "onnn,nb7vpq904m"; + // reg = <0x1c>; + + // vcc-supply = <&vreg_l15b_1p8>; + + // retimer-switch; + // orientation-switch; + + // ports { + // #address-cells = <1>; + // #size-cells = <0>; + + // port@0 { + // reg = <0>; + + // redriver_ss_out: endpoint { + // remote-endpoint = <&pmic_glink_ss_in>; + // }; + // }; + + // port@1 { + // reg = <1>; + + // redriver_ss_in: endpoint { + // data-lanes = <3 2 1 0>; + // remote-endpoint = <&usb_dp_qmpphy_out>; + // }; + // }; + // }; + // }; + + /* No driver. aw883xx chip id = 2066 */ + + // audio-codec@34 { + // compatible = "awinic,aw88395"; + // reg = <0x34>; + // #sound-dai-cells = <0>; + // reset-gpios = <&tlmm 103 GPIO_ACTIVE_HIGH>; + // awinic,audio-channel = <0>; + // awinic,sync-flag; + // }; + + // audio-codec@35 { + // compatible = "awinic,aw88395"; + // reg = <0x35>; + // #sound-dai-cells = <0>; + // reset-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + // awinic,audio-channel = <1>; + // awinic,sync-flag; + // }; + + // typec-mux@42 { + // compatible = "fcs,fsa4480"; + // reg = <0x42>; + + // vcc-supply = <&vreg_bob1>; + + // mode-switch; + // orientation-switch; + + // port { + // fsa4480_sbu_mux: endpoint { + // remote-endpoint = <&pmic_glink_sbu>; + // }; + // }; + // }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&hdmi_out_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1e_0p88>; + status = "okay"; +}; + +&mdss_dsi1 { + vdda-supply = <&vreg_l3e_1p2>; + status = "okay"; + + panel@0 { + compatible = "odin,panel"; + reg = <0>; + + // pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>; + // pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>; + // pinctrl-names = "default", "sleep"; + + // vci-supply = <&vreg_l13b_3p0>; + // vdd-supply = <&vreg_l11b_1p2>; + // vddio-supply = <&vreg_l12b_1p8>; + + // backlight = <&backlight>; + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi1_out>; + }; + }; + }; +}; + +&mdss_dsi1_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi1_phy { + vdds-supply = <&vreg_l1e_0p88>; + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; +}; + +&pcie0 { + /* TODO: switch to subnode for power sequence */ + vdda-supply = <&wlan_regulator>; + + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + /* pmk8550_sleep_clk should be in the pcie wlan device subnode */ + pinctrl-0 = <&pcie0_default_state>, <&pmk8550_sleep_clk>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + + +&pm8550_gpios { + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio12"; + function = "normal"; + input-enable; + output-disable; + bias-pull-up; + power-source = <1>; /* 1.8 V */ + }; + + pwm_out_default: pwm-out-default-state { + pins = "gpio8"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + }; +}; + +&pm8550_pwm { + status = "okay"; + + // multi-led { + // color = ; + // function = LED_FUNCTION_STATUS; + + // #address-cells = <1>; + // #size-cells = <0>; + + // led@1 { + // reg = <1>; + // color = ; + // }; + + // led@2 { + // reg = <2>; + // color = ; + // }; + + // led@3 { + // reg = <3>; + // color = ; + // }; + // }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + +&pmk8550_gpios { + pmk8550_sleep_clk: sleep-clk-state { + pins = "gpio3"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + }; +}; + +&pmk8550_rtc { + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "offset"; + + status = "okay"; +}; + +&pmk8550_sdam_2 { + status = "okay"; + + rtc_offset: rtc-offset@bc { + reg = <0xbc 0x4>; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8550/ayn/odin2/adsp.mdt", + "qcom/sm8550/ayn/odin2/adsp_dtb.mdt"; + status = "okay"; +}; + +// &remoteproc_cdsp { +// firmware-name = "qcom/sm8550/cdsp.mbn", +// "qcom/sm8550/cdsp_dtb.mbn"; +// status = "okay"; +// }; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + bus-width = <4>; + no-sdio; + no-mmc; + + /* SDR104 does seem to be working */ + /delete-property/ sdhci-caps-mask; + qcom,dll-config = <0x0007442c>; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +// &swr0 { +// status = "okay"; + +// /* WSA8845, Speaker North */ +// north_spkr: speaker@0,0 { +// compatible = "sdw20217020400"; +// reg = <0 0>; +// pinctrl-names = "default"; +// pinctrl-0 = <&spkr_1_sd_n_active>; +// powerdown-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>; +// #sound-dai-cells = <0>; +// sound-name-prefix = "SpkrLeft"; +// vdd-1p8-supply = <&vreg_l15b_1p8>; +// vdd-io-supply = <&vreg_l3g_1p2>; +// }; + +// /* WSA8845, Speaker South */ +// south_spkr: speaker@0,1 { +// compatible = "sdw20217020400"; +// reg = <0 1>; +// pinctrl-names = "default"; +// pinctrl-0 = <&spkr_2_sd_n_active>; +// powerdown-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>; +// #sound-dai-cells = <0>; +// sound-name-prefix = "SpkrRight"; +// vdd-1p8-supply = <&vreg_l15b_1p8>; +// vdd-io-supply = <&vreg_l3g_1p2>; +// }; +// }; + +// &swr1 { +// status = "okay"; + +// /* WCD9385 RX */ +// wcd_rx: codec@0,4 { +// compatible = "sdw20217010d00"; +// reg = <0 4>; +// qcom,rx-port-mapping = <1 2 3 4 5>; +// }; +// }; + +// &swr2 { +// status = "okay"; + +// /* WCD9385 TX */ +// wcd_tx: codec@0,3 { +// compatible = "sdw20217010d00"; +// reg = <0 3>; +// qcom,tx-port-mapping = <1 1 2 3>; +// }; +// }; + +&tlmm { + gpio-reserved-ranges = <32 8>; + + ts_reset_default: ts-reset-default-state { + pins = "gpio24"; + function = "gpio"; + bias-pull-up; + drive-strength = <8>; + }; + + ts_int_default: ts-int-default-state { + pins = "gpio25"; + function = "gpio"; + bias-pull-up; + drive-strength = <8>; + }; + + ts_reset_sleep: ts-reset-sleep-state { + pins = "gpio24"; + function = "gpio"; + bias-pull-down; + drive-strength = <2>; + }; + + ts_int_sleep: ts-int-sleep-state { + pins = "gpio25"; + function = "gpio"; + bias-pull-down; + drive-strength = <2>; + }; + + bt_default: bt-default-state { + bt-en-pins { + pins = "gpio81"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins = "gpio82"; + function = "gpio"; + bias-pull-down; + }; + }; + + usb0_sbu_default: usb0-sbu-state { + oe-n-pins { + pins = "gpio140"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + output-high; + }; + + sel-pins { + pins = "gpio141"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + }; + // sde_dp_active_state: sde-dp-active-state { + // pins = "gpio140", "gpio141"; + // function = "gpio"; + // bias-pull-up; + // drive-strength = <16>; + // output-high; + // }; + + // sde_dsi_active: sde-dsi-active-state { + // pins = "gpio133"; + // function = "gpio"; + // drive-strength = <8>; + // bias-disable; + // }; + + // sde_dsi_suspend: sde-dsi-suspend-state { + // pins = "gpio133"; + // function = "gpio"; + // drive-strength = <2>; + // bias-pull-down; + // }; + + // sde_te_active: sde-te-active-state { + // pins = "gpio86"; + // function = "mdp_vsync"; + // drive-strength = <2>; + // bias-pull-down; + // }; + + // sde_te_suspend: sde-te-suspend-state { + // pins = "gpio86"; + // function = "mdp_vsync"; + // drive-strength = <2>; + // bias-pull-down; + // }; + + // wcd_default: wcd-reset-n-active-state { + // pins = "gpio108"; + // function = "gpio"; + // drive-strength = <16>; + // bias-disable; + // output-low; + // }; +}; + +&uart7 { + status = "okay"; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_s4e_0p95>; + vdddig-supply = <&vreg_s4e_0p95>; + vddrfa0p8-supply = <&vreg_s4e_0p95>; + vddrfa1p2-supply = <&vreg_s4g_1p25>; + vddrfa1p9-supply = <&vreg_s6g_1p86>; + + max-speed = <3200000>; + + enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&bt_default>; + pinctrl-names = "default"; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1g_1p2>; + vccq-max-microamp = <1200000>; + vdd-hba-supply = <&vreg_l3g_1p2>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "otg"; + usb-role-switch; + maximum-speed = "super-speed-plus-gen2x1"; + + port { + usb_1_role_switch: endpoint { + remote-endpoint = <&pmic_glink_con0_hs>; + }; + }; +}; + +// &usb_1_dwc3_hs { +// remote-endpoint = <&pmic_glink_hs_in>; +// }; + +&usb_1_dwc3_ss { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&pm8550b_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3f_0p88>; + + orientation-switch; + + status = "okay"; +}; + +&usb_dp_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + +&xo_board { + clock-frequency = <76800000>; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 7bafb3d88d69..d6713b041305 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -285,9 +285,9 @@ compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <800>; + entry-latency-us = <550>; exit-latency-us = <750>; - min-residency-us = <4090>; + min-residency-us = <6700>; local-timer-stop; }; @@ -296,27 +296,37 @@ idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <600>; - exit-latency-us = <1550>; - min-residency-us = <4791>; + exit-latency-us = <1300>; + min-residency-us = <8136>; local-timer-stop; }; + + PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-plus-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <500>; + exit-latency-us = <1350>; + min-residency-us = <7480>; + local-timer-stop; + }; }; domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x41000044>; - entry-latency-us = <1050>; - exit-latency-us = <2500>; - min-residency-us = <5309>; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; }; CLUSTER_SLEEP_1: cluster-sleep-1 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x4100c344>; - entry-latency-us = <2700>; - exit-latency-us = <3500>; - min-residency-us = <13959>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; }; }; }; @@ -343,7 +353,15 @@ memory@a0000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ - reg = <0 0xa0000000 0 0>; + // reg = <0 0xa0000000 0 0>; + reg = <0x0 0x80000000 0x0 0xe00000 + 0x0 0x811d0000 0x0 0x56e30000 + 0x0 0xd8140000 0x0 0x20000 + 0x0 0xd8800000 0x0 0x0 + 0x0 0xe1bb0000 0x0 0x1e450000 + 0x8 0x80000000 0x0 0x39a00000 + 0x9 0x80000000 0x1 0x80000000 + 0x8 0xc0000000 0x0 0xc0000000>; }; pmu { @@ -400,7 +418,7 @@ CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; + domain-idle-states = <&PRIME_CPU_SLEEP_0>; }; CLUSTER_PD: power-domain-cluster { @@ -453,7 +471,12 @@ /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ aop_config_merged_mem: aop-config-merged-region@81c80000 { - reg = <0 0x81c80000 0 0x74000>; + reg = <0 0x81c80000 0 0x64000>; + no-map; + }; + + uefi_log: uefi-log@81ce4000 { + reg = <0 0x81ce4000 0 0x10000>; no-map; }; @@ -801,6 +824,7 @@ dma-channels = <12>; dma-channel-mask = <0x3e>; iommus = <&apps_smmu 0x436 0>; + dma-coherent; status = "disabled"; }; @@ -812,6 +836,7 @@ clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; iommus = <&apps_smmu 0x423 0>; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled"; @@ -1311,6 +1336,7 @@ dma-channels = <12>; dma-channel-mask = <0x1e>; iommus = <&apps_smmu 0xb6 0>; + dma-coherent; status = "disabled"; }; @@ -1324,6 +1350,7 @@ iommus = <&apps_smmu 0xa3 0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; interconnect-names = "qup-core"; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled"; @@ -2053,6 +2080,7 @@ pinctrl-names = "default"; pinctrl-0 = <&wsa2_swr_active>; #sound-dai-cells = <1>; + status = "disabled"; }; swr3: soundwire-controller@6ab0000 { @@ -2099,6 +2127,7 @@ pinctrl-names = "default"; pinctrl-0 = <&rx_swr_active>; #sound-dai-cells = <1>; + status = "disabled"; }; swr1: soundwire-controller@6ad0000 { @@ -2145,6 +2174,7 @@ pinctrl-names = "default"; pinctrl-0 = <&tx_swr_active>; #sound-dai-cells = <1>; + status = "disabled"; }; lpass_wsamacro: codec@6b00000 { @@ -2164,6 +2194,7 @@ pinctrl-names = "default"; pinctrl-0 = <&wsa_swr_active>; #sound-dai-cells = <1>; + status = "disabled"; }; swr0: soundwire-controller@6b10000 { @@ -2235,6 +2266,7 @@ #clock-cells = <0>; clock-output-names = "fsgen"; #sound-dai-cells = <1>; + status = "disabled"; }; lpass_tlmm: pinctrl@6e80000 { @@ -2249,6 +2281,8 @@ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; clock-names = "core", "audio"; + status = "disabled"; + tx_swr_active: tx-swr-active-state { clk-pins { pins = "gpio0"; @@ -2841,6 +2875,172 @@ #power-domain-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43050a01", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = ; + }; + + opp-615000000 { + opp-hz = /bits/ 64 <615000000>; + opp-level = ; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = ; + }; + + opp-475000000 { + opp-hz = /bits/ 64 <475000000>; + opp-level = ; + }; + + opp-401000000 { + opp-hz = /bits/ 64 <401000000>; + opp-level = ; + }; + + opp-348000000 { + opp-hz = /bits/ 64 <348000000>; + opp-level = ; + }; + + opp-295000000 { + opp-hz = /bits/ 64 <295000000>; + opp-level = ; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-43050a01", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8550-snps-eusb2-phy"; reg = <0x0 0x088e3000 0x0 0x154>; @@ -3692,6 +3892,7 @@ , , ; + dma-coherent; }; intc: interrupt-controller@17100000 { diff --git a/arch/arm64/configs/odin2_defconfig b/arch/arm64/configs/odin2_defconfig new file mode 100644 index 000000000000..5509810cf92c --- /dev/null +++ b/arch/arm64/configs/odin2_defconfig @@ -0,0 +1,1127 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_WATCH_QUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_FULL=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_PRELOAD=y +CONFIG_BPF_PRELOAD_UMD=y +CONFIG_PREEMPT=y +CONFIG_PREEMPT_DYNAMIC=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_RCU_EXPERT=y +CONFIG_RCU_BOOST=y +CONFIG_RCU_LAZY=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=21 +CONFIG_PRINTK_INDEX=y +CONFIG_UCLAMP_TASK=y +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_UCLAMP_TASK_GROUP=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_MISC=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_INITRAMFS_SOURCE="~/odin2/initramfs-linux-latest.cpio" +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_INITRAMFS_COMPRESSION_ZSTD=y +CONFIG_PROFILING=y +CONFIG_KEXEC_FILE=y +CONFIG_CRASH_DUMP=y +CONFIG_ARCH_QCOM=y +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_CLUSTER=y +CONFIG_NUMA=y +CONFIG_HZ_300=y +CONFIG_PARAVIRT_TIME_ACCOUNTING=y +CONFIG_COMPAT=y +CONFIG_COMPAT_ALIGNMENT_FIXUPS=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y +CONFIG_ARM64_PMEM=y +CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_MODULE_REGION_FULL is not set +CONFIG_CMDLINE="clk_ignore_unused pd_ignore_unused panic=30 audit=0 loglevel=7 allow_mismatched_32bit_el0 root=PARTLABEL=arch rw rootfstype=btrfs drm.debug=0x100" +CONFIG_CMDLINE_FORCE=y +CONFIG_ENERGY_MODEL=y +CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y +CONFIG_ARM_QCOM_CPUFREQ_HW=y +CONFIG_ACPI=y +CONFIG_ACPI_FPDT=y +CONFIG_ACPI_HOTPLUG_MEMORY=y +CONFIG_ACPI_BGRT=y +CONFIG_ACPI_HMAT=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_EINJ=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y +CONFIG_LOCK_EVENT_COUNTS=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y +CONFIG_BLK_DEV_ZONED=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_BLK_DEV_THROTTLING_LOW=y +CONFIG_BLK_WBT=y +CONFIG_BLK_CGROUP_IOLATENCY=y +CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_CGROUP_IOPRIO=y +CONFIG_BLK_SED_OPAL=y +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y +CONFIG_BINFMT_MISC=y +CONFIG_ZSWAP=y +CONFIG_ZSWAP_DEFAULT_ON=y +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y +CONFIG_ZSMALLOC_STAT=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_PAGE_REPORTING=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_MEMORY_FAILURE=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_READ_ONLY_THP_FOR_FS=y +CONFIG_CMA=y +CONFIG_CMA_DEBUGFS=y +CONFIG_CMA_SYSFS=y +CONFIG_IDLE_PAGE_TRACKING=y +CONFIG_ZONE_DEVICE=y +CONFIG_DEVICE_PRIVATE=y +CONFIG_ANON_VMA_NAME=y +CONFIG_USERFAULTFD=y +CONFIG_LRU_GEN=y +CONFIG_LRU_GEN_ENABLED=y +CONFIG_DAMON=y +CONFIG_DAMON_VADDR=y +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_DBGFS=y +CONFIG_DAMON_RECLAIM=y +CONFIG_DAMON_LRU_SORT=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_TABLES=y +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=y +CONFIG_NFT_CT=y +CONFIG_NFT_CONNLIMIT=y +CONFIG_NFT_LOG=y +CONFIG_NFT_LIMIT=y +CONFIG_NFT_MASQ=y +CONFIG_NFT_REDIR=y +CONFIG_NFT_NAT=y +CONFIG_NFT_TUNNEL=y +CONFIG_NFT_QUEUE=y +CONFIG_NFT_QUOTA=y +CONFIG_NFT_REJECT=y +CONFIG_NFT_COMPAT=y +CONFIG_NFT_HASH=y +CONFIG_NFT_SOCKET=y +CONFIG_NFT_OSF=y +CONFIG_NFT_TPROXY=y +CONFIG_NFT_SYNPROXY=y +CONFIG_NFT_DUP_NETDEV=y +CONFIG_NFT_FWD_NETDEV=y +CONFIG_NFT_REJECT_NETDEV=y +CONFIG_NF_FLOW_TABLE_INET=y +CONFIG_NF_FLOW_TABLE=y +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NETFILTER_XT_MATCH_BPF=y +CONFIG_NETFILTER_XT_MATCH_CGROUP=y +CONFIG_NETFILTER_XT_MATCH_CLUSTER=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_CPU=y +CONFIG_NETFILTER_XT_MATCH_DCCP=y +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPCOMP=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_IPVS=y +CONFIG_NETFILTER_XT_MATCH_L2TP=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_NFACCT=y +CONFIG_NETFILTER_XT_MATCH_OSF=y +CONFIG_NETFILTER_XT_MATCH_OWNER=y +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_RATEEST=y +CONFIG_NETFILTER_XT_MATCH_REALM=y +CONFIG_NETFILTER_XT_MATCH_RECENT=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_IP_VS=y +CONFIG_NFT_DUP_IPV4=y +CONFIG_NFT_FIB_IPV4=y +CONFIG_NF_TABLES_ARP=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_RPFILTER=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_SYNPROXY=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y +CONFIG_NFT_FIB_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_AH=y +CONFIG_IP6_NF_MATCH_EUI64=y +CONFIG_IP6_NF_MATCH_MH=y +CONFIG_IP6_NF_MATCH_RPFILTER=y +CONFIG_IP6_NF_MATCH_RT=y +CONFIG_IP6_NF_MATCH_SRH=y +CONFIG_IP6_NF_TARGET_HL=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_TARGET_SYNPROXY=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_NAT=y +CONFIG_IP6_NF_TARGET_MASQUERADE=y +CONFIG_IP6_NF_TARGET_NPT=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_REDIRECT=y +CONFIG_BPFILTER=y +CONFIG_BPFILTER_UMH=y +CONFIG_BRIDGE=y +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_VLAN_8021Q=y +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_FQ_CODEL=y +CONFIG_NET_SCH_DEFAULT=y +CONFIG_DEFAULT_FQ_CODEL=y +CONFIG_NET_EMATCH=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_GATE=y +CONFIG_NET_TC_SKB_EXT=y +CONFIG_NET_SWITCHDEV=y +CONFIG_QRTR_SMD=y +CONFIG_QRTR_TUN=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_LEDS=y +CONFIG_BT_MSFTEXT=y +CONFIG_BT_AOSPEXT=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_MAC80211_LEDS=y +CONFIG_RFKILL=y +CONFIG_NFC=y +CONFIG_NFC_NCI=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEAER=y +CONFIG_PCIE_QCOM=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DEVTMPFS_SAFE=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_FW_UPLOAD=y +# CONFIG_QCOM_EBI2 is not set +CONFIG_MHI_BUS_DEBUG=y +CONFIG_MHI_BUS_PCI_GENERIC=y +CONFIG_CONNECTOR=y +CONFIG_ARM_SCMI_PROTOCOL=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_DMI_SYSFS=y +CONFIG_SYSFB_SIMPLEFB=y +CONFIG_EFI_CAPSULE_LOADER=y +CONFIG_ZRAM=y +CONFIG_ZRAM_DEF_COMP_ZSTD=y +CONFIG_ZRAM_WRITEBACK=y +CONFIG_ZRAM_MULTI_COMP=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=y +CONFIG_VIRTIO_BLK=y +CONFIG_BLK_DEV_NVME=y +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_HWMON=y +CONFIG_QCOM_COINCELL=y +CONFIG_QCOM_FASTRPC=y +CONFIG_SRAM=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_UACCE=y +CONFIG_RAID_ATTRS=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_SAS_LIBSAS=y +CONFIG_SCSI_SAS_ATA=y +CONFIG_ATA=y +# CONFIG_ATA_VERBOSE_ERROR is not set +# CONFIG_ATA_ACPI is not set +# CONFIG_SATA_PMP is not set +# CONFIG_ATA_SFF is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_DEBUG=y +CONFIG_DM_MIRROR=y +CONFIG_DM_ZERO=y +CONFIG_DM_AUDIT=y +CONFIG_TARGET_CORE=y +CONFIG_TCM_IBLOCK=y +CONFIG_TCM_PSCSI=y +CONFIG_NETDEVICES=y +CONFIG_IFB=y +CONFIG_MACVLAN=y +CONFIG_MACVTAP=y +CONFIG_TUN=y +CONFIG_VETH=y +CONFIG_VIRTIO_NET=y +CONFIG_MHI_NET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ASIX is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DAVICOM is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FUNGIBLE is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_ADI is not set +# CONFIG_NET_VENDOR_LITEX is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +CONFIG_R8169=y +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WANGXUN is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_QCOM_IPA=y +CONFIG_USB_RTL8152=y +CONFIG_USB_USBNET=y +# CONFIG_USB_NET_AX8817X is not set +# CONFIG_USB_NET_AX88179_178A is not set +CONFIG_USB_NET_CDC_EEM=y +CONFIG_USB_NET_SMSC95XX=y +# CONFIG_USB_NET_NET1080 is not set +CONFIG_USB_NET_RNDIS_HOST=y +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_ATH11K=y +CONFIG_ATH11K_PCI=y +CONFIG_ATH11K_DEBUG=y +CONFIG_ATH12K=y +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +# CONFIG_WLAN_VENDOR_MICROCHIP is not set +# CONFIG_WLAN_VENDOR_PURELIFI is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +# CONFIG_RTL_CARDS is not set +CONFIG_RTW88=y +CONFIG_RTW88_8821CU=y +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_SILABS is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +CONFIG_WWAN=y +CONFIG_MHI_WWAN_CTRL=y +CONFIG_MHI_WWAN_MBIM=y +CONFIG_INPUT_MATRIXKMAP=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_ADC=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_MOUSE_ELAN_I2C=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=y +CONFIG_TOUCHSCREEN_GOODIX=y +CONFIG_TOUCHSCREEN_ELAN=y +CONFIG_TOUCHSCREEN_EDT_FT5X06=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_PM8941_PWRKEY=y +CONFIG_INPUT_PM8XXX_VIBRATOR=y +CONFIG_INPUT_PWM_BEEPER=y +CONFIG_INPUT_PWM_VIBRA=y +CONFIG_RMI4_I2C=y +CONFIG_RMI4_F34=y +CONFIG_RMI4_F3A=y +CONFIG_RMI4_F54=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_AMBAKMI=y +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SERIAL_QCOM_GENI=y +CONFIG_SERIAL_QCOM_GENI_CONSOLE=y +CONFIG_RPMSG_TTY=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS=y +CONFIG_TCG_CRB=y +CONFIG_TCG_FTPM_TEE=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_NVIDIA_GPU=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_QCOM_CCI=y +CONFIG_I2C_QCOM_GENI=y +CONFIG_I2C_QUP=y +CONFIG_I2C_SLAVE=y +CONFIG_SPI=y +CONFIG_SPI_MEM=y +CONFIG_SPI_CADENCE_QUADSPI=y +CONFIG_SPI_PL022=y +CONFIG_SPI_QCOM_QSPI=y +CONFIG_SPI_QUP=y +CONFIG_SPI_QCOM_GENI=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPMI=y +# CONFIG_PTP_1588_CLOCK_KVM is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_MSM=y +CONFIG_PINCTRL_SDM845=y +CONFIG_PINCTRL_SM8250=y +CONFIG_PINCTRL_SM8350=y +CONFIG_PINCTRL_SM8450=y +CONFIG_PINCTRL_SM8550=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_LPASS_LPI=y +CONFIG_PINCTRL_SM8250_LPASS_LPI=y +CONFIG_PINCTRL_SM8350_LPASS_LPI=y +CONFIG_GPIO_ALTERA=y +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_WCD934X=y +CONFIG_GPIO_XGENE=y +CONFIG_GPIO_MAX732X=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_RESET_QCOM_PON=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_NVMEM_REBOOT_MODE=y +CONFIG_BATTERY_QCOM_BATTMGR=y +CONFIG_BATTERY_SBS=y +CONFIG_BATTERY_BQ27XXX=y +CONFIG_BATTERY_MAX17042=y +CONFIG_CHARGER_BQ25890=y +CONFIG_CHARGER_BQ25980=y +CONFIG_SENSORS_ARM_SCMI=y +CONFIG_SENSORS_ARM_SCPI=y +CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_JC42=y +CONFIG_SENSORS_LM75=y +CONFIG_SENSORS_LM90=y +CONFIG_SENSORS_PWM_FAN=y +CONFIG_SENSORS_INA2XX=y +CONFIG_SENSORS_INA3221=y +CONFIG_THERMAL_NETLINK=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_GENERIC_ADC_THERMAL=y +CONFIG_QCOM_TSENS=y +CONFIG_QCOM_SPMI_ADC_TM5=y +CONFIG_QCOM_SPMI_TEMP_ALARM=y +CONFIG_QCOM_LMH=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_SYSFS=y +CONFIG_ARM_SP805_WATCHDOG=y +CONFIG_ARM_SBSA_WATCHDOG=y +CONFIG_DW_WATCHDOG=y +CONFIG_QCOM_WDT=y +CONFIG_ARM_SMC_WATCHDOG=y +CONFIG_PM8916_WATCHDOG=y +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_MFD_RK8XX_I2C=y +CONFIG_MFD_RK8XX_SPI=y +CONFIG_MFD_TI_AM335X_TSCADC=y +CONFIG_MFD_WCD934X=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_QCOM_REFGEN=y +CONFIG_REGULATOR_QCOM_RPMH=y +CONFIG_REGULATOR_QCOM_SMD_RPM=y +CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_QCOM_USB_VBUS=y +CONFIG_REGULATOR_VCTRL=y +CONFIG_REGULATOR_QCOM_LABIBB=y +CONFIG_RC_CORE=y +CONFIG_LIRC=y +# CONFIG_RC_MAP is not set +CONFIG_RC_DECODERS=y +CONFIG_RC_DEVICES=y +CONFIG_IR_SPI=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_VIDEO_ADV_DEBUG=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y +CONFIG_VIDEO_MUX=y +CONFIG_VIDEO_QCOM_CAMSS=y +CONFIG_VIDEO_QCOM_VENUS=y +CONFIG_VIDEO_HI846=y +CONFIG_DRM=y +CONFIG_DRM_DP_AUX_CHARDEV=y +CONFIG_DRM_DP_CEC=y +CONFIG_DRM_MSM=y +# CONFIG_DRM_MSM_MDP4 is not set +# CONFIG_DRM_MSM_MDP5 is not set +# CONFIG_DRM_MSM_DSI_28NM_PHY is not set +# CONFIG_DRM_MSM_DSI_20NM_PHY is not set +# CONFIG_DRM_MSM_DSI_28NM_8960_PHY is not set +# CONFIG_DRM_MSM_DSI_14NM_PHY is not set +# CONFIG_DRM_MSM_HDMI is not set +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_EDP=y +CONFIG_DRM_PANEL_NOVATEK_NT36523=y +CONFIG_DRM_PANEL_VISIONOX_R66451=y +CONFIG_DRM_PANEL_XIAOMI_EA8182=y +CONFIG_DRM_PANEL_XIAOMI_M82=y +CONFIG_DRM_PANEL_AYN_ODIN2=y +CONFIG_DRM_DISPLAY_CONNECTOR=y +CONFIG_DRM_LONTIUM_LT8912B=y +CONFIG_DRM_LONTIUM_LT9611=y +CONFIG_DRM_SIMPLE_BRIDGE=y +CONFIG_DRM_SIMPLEDRM=y +CONFIG_FB=y +CONFIG_FB_EFI=y +CONFIG_FB_EARLY=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_KTZ8866=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_QCOM_WLED=y +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_HDA_INTEL=y +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_CODEC_HDMI=y +CONFIG_SND_HDA_GENERIC=y +# CONFIG_SND_SPI is not set +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_AUDIO_MIDI_V2=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_QCOM=y +CONFIG_SND_SOC_SDM845=y +CONFIG_SND_SOC_SM8250=y +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_OF=y +CONFIG_SND_SOC_AW88395=y +CONFIG_SND_SOC_CS35L41_I2C=y +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y +CONFIG_SND_SOC_SIMPLE_MUX=y +CONFIG_SND_SOC_WCD934X=y +CONFIG_SND_SOC_LPASS_WSA_MACRO=y +CONFIG_SND_SOC_LPASS_VA_MACRO=y +CONFIG_SND_SOC_LPASS_RX_MACRO=y +CONFIG_SND_SOC_LPASS_TX_MACRO=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_AUDIO_GRAPH_CARD=y +CONFIG_SND_AUDIO_GRAPH_CARD2=y +CONFIG_HIDRAW=y +CONFIG_HID_LOGITECH_DJ=y +CONFIG_HID_MULTITOUCH=y +CONFIG_HID_RMI=y +CONFIG_I2C_HID_ACPI=y +CONFIG_I2C_HID_OF=y +CONFIG_USB_ULPI_BUS=y +CONFIG_USB_CONN_GPIO=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OTG=y +CONFIG_USB_MON=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_UAS=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_ULPI=y +# CONFIG_USB_DWC3_PCI is not set +# CONFIG_USB_DWC3_HAPS is not set +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=y +CONFIG_USB_SERIAL_CH341=y +CONFIG_USB_SERIAL_CP210X=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_OPTION=y +CONFIG_USB_ONBOARD_HUB=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_TCM=y +CONFIG_TYPEC=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_QCOM_PMIC=y +CONFIG_TYPEC_UCSI=y +CONFIG_UCSI_PMIC_GLINK=y +CONFIG_TYPEC_MUX_FSA4480=y +CONFIG_TYPEC_MUX_GPIO_SBU=y +CONFIG_TYPEC_DP_ALTMODE=y +CONFIG_MMC=y +CONFIG_MMC_CRYPTO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_HSQ=y +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFS_BSG=y +CONFIG_SCSI_UFS_CRYPTO=y +CONFIG_SCSI_UFS_HWMON=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_SCSI_UFS_QCOM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_MULTICOLOR=y +CONFIG_LEDS_LM3692X=y +CONFIG_LEDS_PCA9532=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_QCOM_LPG=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_EDAC=y +CONFIG_EDAC_GHES=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_PM8XXX=y +CONFIG_DMADEVICES=y +CONFIG_FSL_EDMA=y +CONFIG_MV_XOR_V2=y +CONFIG_PL330_DMA=y +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_GPI_DMA=y +CONFIG_QCOM_HIDMA_MGMT=y +CONFIG_QCOM_HIDMA=y +CONFIG_UDMABUF=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_SYSFS_STATS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_VFIO=y +CONFIG_VIRT_DRIVERS=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +CONFIG_STAGING=y +# CONFIG_SURFACE_PLATFORMS is not set +CONFIG_COMMON_CLK_SCMI=y +CONFIG_COMMON_CLK_SCPI=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_COMMON_CLK_QCOM=y +CONFIG_QCOM_CLK_SMD_RPM=y +CONFIG_QCOM_CLK_RPMH=y +CONFIG_SC_DISPCC_8280XP=y +CONFIG_SA_GPUCC_8775P=y +CONFIG_SC_GCC_7180=y +CONFIG_SC_GCC_7280=y +CONFIG_SC_GCC_8180X=y +CONFIG_SC_GPUCC_8280XP=y +CONFIG_SC_LPASSCC_8280XP=y +CONFIG_SDM_CAMCC_845=y +CONFIG_SDM_GPUCC_845=y +CONFIG_SDM_VIDEOCC_845=y +CONFIG_SDM_DISPCC_845=y +CONFIG_SDM_LPASSCC_845=y +CONFIG_SM_CAMCC_8250=y +CONFIG_SM_CAMCC_8550=y +CONFIG_SM_DISPCC_8250=y +CONFIG_SM_DISPCC_8550=y +CONFIG_SM_GCC_8450=y +CONFIG_SM_GPUCC_8250=y +CONFIG_SM_GPUCC_8350=y +CONFIG_SM_GPUCC_8550=y +CONFIG_SM_TCSRCC_8550=y +CONFIG_SM_VIDEOCC_8250=y +CONFIG_SM_VIDEOCC_8350=y +CONFIG_SM_VIDEOCC_8550=y +CONFIG_SPMI_PMIC_CLKDIV=y +CONFIG_QCOM_HFPLL=y +CONFIG_CLK_GFM_LPASS_SM8250=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_MAILBOX=y +CONFIG_ARM_MHU=y +CONFIG_PLATFORM_MHU=y +CONFIG_PCC=y +CONFIG_QCOM_APCS_IPC=y +CONFIG_QCOM_IPCC=y +CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y +CONFIG_QCOM_IOMMU=y +CONFIG_REMOTEPROC=y +CONFIG_REMOTEPROC_CDEV=y +CONFIG_QCOM_Q6V5_ADSP=y +CONFIG_QCOM_Q6V5_MSS=y +CONFIG_QCOM_Q6V5_PAS=y +CONFIG_QCOM_SYSMON=y +CONFIG_QCOM_WCNSS_PIL=y +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_CTRL=y +CONFIG_RPMSG_NS=y +CONFIG_RPMSG_QCOM_GLINK_RPM=y +CONFIG_RPMSG_QCOM_GLINK_SMEM=y +CONFIG_RPMSG_QCOM_SMD=y +CONFIG_SOUNDWIRE=y +CONFIG_SOUNDWIRE_QCOM=y +CONFIG_QCOM_AOSS_QMP=y +CONFIG_QCOM_COMMAND_DB=y +CONFIG_QCOM_GENI_SE=y +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_OCMEM=y +CONFIG_QCOM_PMIC_GLINK=y +CONFIG_QCOM_RMTFS_MEM=y +CONFIG_QCOM_RPMH=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SMD_RPM=y +CONFIG_QCOM_SMP2P=y +CONFIG_QCOM_SMSM=y +CONFIG_QCOM_SOCINFO=y +CONFIG_QCOM_SPM=y +CONFIG_QCOM_STATS=y +CONFIG_QCOM_APR=y +CONFIG_QCOM_ICC_BWMON=y +CONFIG_QCOM_DUMP_XBL_LOG=y +CONFIG_QCOM_CPR=y +CONFIG_QCOM_RPMHPD=y +CONFIG_QCOM_RPMPD=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_DEVFREQ_GOV_PASSIVE=y +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_EXTCON_QCOM_SPMI_MISC=y +CONFIG_EXTCON_USB_GPIO=y +CONFIG_MEMORY=y +CONFIG_IIO=y +CONFIG_IIO_BUFFER_CB=y +CONFIG_IIO_BUFFER_DMAENGINE=y +CONFIG_IIO_BUFFER_HW_CONSUMER=y +CONFIG_IIO_CONFIGFS=y +CONFIG_MAX9611=y +CONFIG_QCOM_SPMI_RRADC=y +CONFIG_QCOM_SPMI_IADC=y +CONFIG_QCOM_SPMI_VADC=y +CONFIG_QCOM_SPMI_ADC5=y +CONFIG_TI_ADS1015=y +CONFIG_TI_AM335X_ADC=y +CONFIG_IIO_ST_LSM6DSX=y +CONFIG_SENSORS_ISL29018=y +CONFIG_VCNL4000=y +CONFIG_MPL3115=y +CONFIG_PWM=y +CONFIG_QCOM_PDC=y +CONFIG_QCOM_MPM=y +CONFIG_RESET_QCOM_AOSS=y +CONFIG_RESET_QCOM_PDC=y +CONFIG_PHY_QCOM_QMP=y +CONFIG_PHY_QCOM_QMP_USB_LEGACY=y +CONFIG_PHY_QCOM_QUSB2=y +CONFIG_PHY_QCOM_SNPS_EUSB2=y +CONFIG_PHY_QCOM_EUSB2_REPEATER=y +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y +CONFIG_ARM_CCI_PMU=y +CONFIG_ARM_CCN=y +CONFIG_ARM_CMN=y +CONFIG_ARM_SMMU_V3_PMU=y +CONFIG_ARM_DSU_PMU=y +CONFIG_QCOM_L2_PMU=y +CONFIG_QCOM_L3_PMU=y +CONFIG_ARM_SPE_PMU=y +CONFIG_ARM_DMC620_PMU=y +CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_BINDERFS=y +CONFIG_NVMEM_LAYOUT_SL28_VPD=y +CONFIG_NVMEM_QCOM_QFPROM=y +CONFIG_NVMEM_RMEM=y +CONFIG_NVMEM_SPMI_SDAM=y +CONFIG_STM=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_SLIM_QCOM_CTRL=y +CONFIG_SLIM_QCOM_NGD_CTRL=y +CONFIG_INTERCONNECT=y +CONFIG_INTERCONNECT_QCOM=y +CONFIG_INTERCONNECT_QCOM_OSM_L3=y +CONFIG_INTERCONNECT_QCOM_SDM845=y +CONFIG_INTERCONNECT_QCOM_SM8250=y +CONFIG_INTERCONNECT_QCOM_SM8350=y +CONFIG_INTERCONNECT_QCOM_SM8450=y +CONFIG_INTERCONNECT_QCOM_SM8550=y +CONFIG_COUNTER=y +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_BTRFS_FS=y +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_CHECK_FS=y +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_ZONEFS_FS=y +CONFIG_FS_DAX=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y +CONFIG_FS_VERITY=y +CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_OVERLAY_FS=y +# CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set +CONFIG_OVERLAY_FS_INDEX=y +CONFIG_OVERLAY_FS_XINO_AUTO=y +CONFIG_OVERLAY_FS_METACOPY=y +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=y +CONFIG_CACHEFILES_ONDEMAND=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +CONFIG_VFAT_FS=y +CONFIG_EXFAT_FS=y +CONFIG_NTFS3_FS=y +CONFIG_NTFS3_LZX_XPRESS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_VMCORE_DEVICE_DUMP=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_INODE64=y +CONFIG_HUGETLBFS=y +CONFIG_EFIVAR_FS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_PMSG=y +CONFIG_PSTORE_RAM=y +CONFIG_EROFS_FS=y +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP_DEFLATE=y +CONFIG_EROFS_FS_ONDEMAND=y +CONFIG_EROFS_FS_PCPU_KTHREAD=y +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_DLM=y +CONFIG_UNICODE=y +CONFIG_SECURITY=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_PCRYPT=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_ECDSA=y +CONFIG_CRYPTO_CURVE25519=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_SM4_GENERIC=y +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_SM3_GENERIC=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_RNG=y +CONFIG_CRYPTO_NHPOLY1305_NEON=y +CONFIG_CRYPTO_CHACHA20_NEON=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_POLY1305_NEON=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64_CE=y +CONFIG_CRYPTO_SHA3_ARM64=y +CONFIG_CRYPTO_SM3_NEON=y +CONFIG_CRYPTO_SM3_ARM64_CE=y +CONFIG_CRYPTO_POLYVAL_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_BS=y +CONFIG_CRYPTO_SM4_ARM64_CE=y +CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y +CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y +CONFIG_CRYPTO_DEV_QCE=y +CONFIG_CRYPTO_DEV_QCOM_RNG=y +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_RAID6_PQ_BENCHMARK is not set +CONFIG_PACKING=y +CONFIG_CORDIC=y +CONFIG_INDIRECT_PIO=y +CONFIG_CRYPTO_LIB_CURVE25519=y +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRC_CCITT=y +CONFIG_CRC7=y +CONFIG_DMA_RESTRICTED_POOL=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_IRQ_POLL=y +CONFIG_PRINTK_TIME=y +CONFIG_STACKTRACE_BUILD_ID=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=4 +CONFIG_CONSOLE_LOGLEVEL_QUIET=1 +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_MISC is not set +CONFIG_DEBUG_INFO_DWARF5=y +CONFIG_DEBUG_INFO_REDUCED=y +CONFIG_DEBUG_INFO_COMPRESSED_ZSTD=y +CONFIG_HEADERS_INSTALL=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_PAGE_POISONING=y +CONFIG_DEBUG_RODATA_TEST=y +CONFIG_DEBUG_WX=y +CONFIG_SHRINKER_DEBUG=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_KFENCE=y +CONFIG_KFENCE_DEFERRABLE=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_HARDLOCKUP_DETECTOR=y +CONFIG_DEBUG_LIST=y +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_TRACE is not set +CONFIG_LATENCYTOP=y +CONFIG_BOOTTIME_TRACING=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_HWLAT_TRACER=y +CONFIG_TIMERLAT_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_USER_EVENTS=y +CONFIG_HIST_TRIGGERS=y +CONFIG_SAMPLES=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_FAULT_INJECTION=y +CONFIG_FAILSLAB=y +CONFIG_FAIL_PAGE_ALLOC=y +CONFIG_FAULT_INJECTION_USERCOPY=y +CONFIG_FAIL_FUTEX=y +CONFIG_FAULT_INJECTION_DEBUG_FS=y +CONFIG_FAULT_INJECTION_CONFIGFS=y +CONFIG_MEMTEST=y diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 7a0220d29a23..20b167a56e8d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1629,10 +1629,6 @@ static int hw_init(struct msm_gpu *gpu) mb(); } - /* Some GPUs are stubborn and take their sweet time to unhalt GBIF! */ - if (adreno_is_a7xx(adreno_gpu) && a6xx_has_gbif(adreno_gpu)) - spin_until(!gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK)); - gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); if (adreno_is_a619_holi(adreno_gpu)) diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index ecb22ea326cb..e338f22f5ab7 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -855,4 +855,13 @@ config DRM_PANEL_XINPENG_XPP055C272 Say Y here if you want to enable support for the Xinpeng XPP055C272 controller for 720x1280 LCD panels with MIPI/RGB/SPI system interfaces. + +config DRM_PANEL_AYN_ODIN2 + tristate "AYN Odin2 video mode panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you have AYN Odin 2. + endmenu diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index e14ce55a0875..dc7d927ee53f 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -87,3 +87,4 @@ obj-$(CONFIG_DRM_PANEL_VISIONOX_VTDR6130) += panel-visionox-vtdr6130.o obj-$(CONFIG_DRM_PANEL_VISIONOX_R66451) += panel-visionox-r66451.o obj-$(CONFIG_DRM_PANEL_WIDECHIPS_WS2401) += panel-widechips-ws2401.o obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o +obj-$(CONFIG_DRM_PANEL_AYN_ODIN2) += panel-odin2.o diff --git a/drivers/gpu/drm/panel/panel-odin2.c b/drivers/gpu/drm/panel/panel-odin2.c new file mode 100644 index 000000000000..a74a9b48a3a4 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-odin2.c @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2023 FIXME +// Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree: +// Copyright (c) 2013, The Linux Foundation. All rights reserved. (FIXME) + +#include +#include +#include +#include + +#include +#include +#include + +struct sim { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + struct gpio_desc *reset_gpio; + bool prepared; +}; + +static inline struct sim *to_sim(struct drm_panel *panel) +{ + return container_of(panel, struct sim, panel); +} + +static void sim_reset(struct sim *ctx) +{ + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + usleep_range(10000, 11000); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + usleep_range(10000, 11000); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + usleep_range(10000, 11000); +} + +static int sim_on(struct sim *ctx) +{ + struct mipi_dsi_device *dsi = ctx->dsi; + struct device *dev = &dsi->dev; + int ret; + + dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00); + mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x31); + mipi_dsi_dcs_write_seq(dsi, 0xd6, 0x00); + + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to exit sleep mode: %d\n", ret); + return ret; + } + msleep(70); + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + dev_err(dev, "Failed to set display on: %d\n", ret); + return ret; + } + + return 0; +} + +static int sim_off(struct sim *ctx) +{ + struct mipi_dsi_device *dsi = ctx->dsi; + struct device *dev = &dsi->dev; + int ret; + + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + + ret = mipi_dsi_dcs_set_display_off(dsi); + if (ret < 0) { + dev_err(dev, "Failed to set display off: %d\n", ret); + return ret; + } + msleep(50); + + ret = mipi_dsi_dcs_enter_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to enter sleep mode: %d\n", ret); + return ret; + } + msleep(120); + + return 0; +} + +static int sim_prepare(struct drm_panel *panel) +{ + struct sim *ctx = to_sim(panel); + struct device *dev = &ctx->dsi->dev; + int ret; + + if (ctx->prepared) + return 0; + + sim_reset(ctx); + + ret = sim_on(ctx); + if (ret < 0) { + dev_err(dev, "Failed to initialize panel: %d\n", ret); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + return ret; + } + + ctx->prepared = true; + return 0; +} + +static int sim_unprepare(struct drm_panel *panel) +{ + struct sim *ctx = to_sim(panel); + struct device *dev = &ctx->dsi->dev; + int ret; + + if (!ctx->prepared) + return 0; + + ret = sim_off(ctx); + if (ret < 0) + dev_err(dev, "Failed to un-initialize panel: %d\n", ret); + + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + + ctx->prepared = false; + return 0; +} + +static const struct drm_display_mode sim_mode = { + .clock = (1080 + 93 + 1 + 47) * (1920 + 40 + 2 + 60) * 60 / 1000, + .hdisplay = 1080, + .hsync_start = 1080 + 93, + .hsync_end = 1080 + 93 + 1, + .htotal = 1080 + 93 + 1 + 47, + .vdisplay = 1920, + .vsync_start = 1920 + 40, + .vsync_end = 1920 + 40 + 2, + .vtotal = 1920 + 40 + 2 + 60, + .width_mm = 0, + .height_mm = 0, +}; + +static int sim_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, &sim_mode); + if (!mode) + return -ENOMEM; + + drm_mode_set_name(mode); + + mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + connector->display_info.width_mm = mode->width_mm; + connector->display_info.height_mm = mode->height_mm; + drm_mode_probed_add(connector, mode); + + return 1; +} + +static const struct drm_panel_funcs sim_panel_funcs = { + .prepare = sim_prepare, + .unprepare = sim_unprepare, + .get_modes = sim_get_modes, +}; + +static int sim_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct sim *ctx; + int ret; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(ctx->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), + "Failed to get reset-gpios\n"); + + ctx->dsi = dsi; + mipi_dsi_set_drvdata(dsi, ctx); + + dsi->lanes = 4; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_CLOCK_NON_CONTINUOUS; + + drm_panel_init(&ctx->panel, dev, &sim_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + ctx->panel.prepare_prev_first = true; + + // ret = drm_panel_of_backlight(&ctx->panel); + // if (ret) + // return dev_err_probe(dev, ret, "Failed to get backlight\n"); + + drm_panel_add(&ctx->panel); + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + dev_err(dev, "Failed to attach to DSI host: %d\n", ret); + drm_panel_remove(&ctx->panel); + return ret; + } + + return 0; +} + +static void sim_remove(struct mipi_dsi_device *dsi) +{ + struct sim *ctx = mipi_dsi_get_drvdata(dsi); + int ret; + + ret = mipi_dsi_detach(dsi); + if (ret < 0) + dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret); + + drm_panel_remove(&ctx->panel); +} + +static const struct of_device_id sim_of_match[] = { + { .compatible = "odin,panel" }, // FIXME + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sim_of_match); + +static struct mipi_dsi_driver sim_driver = { + .probe = sim_probe, + .remove = sim_remove, + .driver = { + .name = "panel-sim", + .of_match_table = sim_of_match, + }, +}; +module_mipi_dsi_driver(sim_driver); + +MODULE_AUTHOR("linux-mdss-dsi-panel-driver-generator "); // FIXME +MODULE_DESCRIPTION("DRM driver for nt35532 video mode dsi panel without DSC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/joystick/Kconfig b/drivers/input/joystick/Kconfig index ac6925ce8366..06c39dd00e56 100644 --- a/drivers/input/joystick/Kconfig +++ b/drivers/input/joystick/Kconfig @@ -344,6 +344,10 @@ config JOYSTICK_MAPLE To compile this as a module choose M here: the module will be called maplecontrol. +config JOYSTICK_ODIN2 + tristate "Ayn Odin2 gamepad" + depends on SERIAL_DEV_BUS + config JOYSTICK_PSXPAD_SPI tristate "PlayStation 1/2 joypads via SPI interface" depends on SPI diff --git a/drivers/input/joystick/Makefile b/drivers/input/joystick/Makefile index 3937535f0098..a665458e4b3e 100644 --- a/drivers/input/joystick/Makefile +++ b/drivers/input/joystick/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_JOYSTICK_JOYDUMP) += joydump.o obj-$(CONFIG_JOYSTICK_MAGELLAN) += magellan.o obj-$(CONFIG_JOYSTICK_MAPLE) += maplecontrol.o obj-$(CONFIG_JOYSTICK_N64) += n64joy.o +obj-$(CONFIG_JOYSTICK_ODIN2) += odin2.o obj-$(CONFIG_JOYSTICK_PSXPAD_SPI) += psxpad-spi.o obj-$(CONFIG_JOYSTICK_PXRC) += pxrc.o obj-$(CONFIG_JOYSTICK_QWIIC) += qwiic-joystick.o diff --git a/drivers/input/joystick/odin2.c b/drivers/input/joystick/odin2.c new file mode 100644 index 000000000000..e049d9f8f2bb --- /dev/null +++ b/drivers/input/joystick/odin2.c @@ -0,0 +1,261 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_DATA_LEN 32 + +#define gamepad_serdev_write_seq(serdev, seq...) \ + do { \ + static const u8 d[] = { seq }; \ + struct device *dev = &serdev->dev; \ + int ret; \ + ret = serdev_device_write_buf(serdev, d, ARRAY_SIZE(d)); \ + if (ret < 0 || ret < ARRAY_SIZE(d)) { \ + dev_err(dev, "Unable to write data\n"); \ + return; \ + } \ + } while (0) + +static const unsigned int keymap[] = { + BTN_DPAD_UP, BTN_DPAD_DOWN, BTN_DPAD_LEFT, BTN_DPAD_RIGHT, + BTN_NORTH, BTN_WEST, BTN_EAST, BTN_SOUTH, + BTN_TL, BTN_TR, BTN_SELECT, BTN_START, + BTN_THUMBL, BTN_THUMBR, BTN_MODE, BTN_BACK +}; + +struct gamepad_data { + u8 header[4]; + u8 frame_number; + u8 command; + u16 data_len; + u8 data[MAX_DATA_LEN]; + u8 checksum; +}; + +struct gamepad_device { + struct device *dev; + struct gpio_desc *en_gpio; + struct input_dev *dev_input; +}; + +static u8 gamepad_data_checksum(const u8 *data, size_t count) +{ + u8 *ptr = data; + u8 ret = data[4]; + for (int i = 5; i < count - 1; i++) { + ret ^= ptr[i]; + } + return ret; +} + +static void gamepad_send_init_sequence(struct serdev_device *serdev) +{ + gamepad_serdev_write_seq(serdev, 0xA5, 0xD3, 0x5A, 0x3D, 0x0, 0x1, 0x2, 0x0, 0x7, 0x1, 0x5); + msleep(100); + gamepad_serdev_write_seq(serdev, 0xA5, 0xD3, 0x5A, 0x3D, 0x1, 0x1, 0x1, 0x0, 0x6, 0x7); + msleep(100); + gamepad_serdev_write_seq(serdev, 0xA5, 0xD3, 0x5A, 0x3D, 0x2, 0x1, 0x1, 0x0, 0x2, 0x0); + msleep(100); + gamepad_serdev_write_seq(serdev, 0xa5, 0xd3, 0x5a, 0x3d, 0x3, 0x01, 0x0a, 0x00, 0x05, 0x01, 0x00, 0x00, + 0x00, 0x28, 0x00, 0x00, 0x00, 0x07, 0x23); + msleep(100); + gamepad_serdev_write_seq(serdev, 0xA5, 0xD3, 0x5A, 0x3D, 0x4, 0x1, 0x1, 0x0, 0x6, 0x2); + msleep(100); + gamepad_serdev_write_seq(serdev, 0xA5, 0xD3, 0x5A, 0x3D, 0x5, 0x1, 0x1, 0x0, 0x2, 0x7); + msleep(100); +} + +static void gamepad_input_handler(struct gamepad_device *dev, struct gamepad_data *data) +{ + static unsigned long prev_states; + unsigned long keys = data->data[0] | (data->data[1] << 8); + unsigned long current_states = keys, changes; + int i; + struct input_dev *indev; + + indev = dev->dev_input; + if(!indev) + return; + + bitmap_xor(&changes, ¤t_states, &prev_states, ARRAY_SIZE(keymap)); + + for_each_set_bit(i, &changes, ARRAY_SIZE(keymap)) { + input_report_key(indev, keymap[i], (current_states & BIT(i))); + } + + input_report_abs(indev, ABS_HAT1X, 0x755 - (data->data[2] | (data->data[3] << 8))); + input_report_abs(indev, ABS_HAT1Y, 0x755 - (data->data[4] | (data->data[5] << 8))); + input_report_abs(indev, ABS_X, 0xaa0 - (data->data[6] | (data->data[7] << 8))); + input_report_abs(indev, ABS_Y, 0xaa0 - (data->data[8] | (data->data[9] << 8))); + input_report_abs(indev, ABS_RX, 0xaa0 - (data->data[10] | (data->data[11] << 8))); + input_report_abs(indev, ABS_RY, 0xaa0 - (data->data[12] | (data->data[13] << 8))); + + input_sync(indev); + prev_states = keys; +} + +static void gamepad_data_handler(struct serdev_device *serdev, struct gamepad_data *data) +{ + struct gamepad_device *dev = serdev_device_get_drvdata(serdev); + switch(data->command) { + case 0x2: + gamepad_input_handler(dev, data); + break; + default: + break; + } +} + +static int gamepad_mcu_uart_rx_bytes(struct serdev_device *serdev, + const u8 *data, + size_t count) +{ + struct device *dev = &serdev->dev; + struct gamepad_data recv_data_buffer; + u8 checksum; + + if (!data || count < 7) { + dev_err(dev, "Invalid packet.\n"); + return count; + } + + checksum = gamepad_data_checksum(data, count); + if (checksum != *(data + count - 1)) { + dev_err(dev, "Packet checksum failed.\n"); + return count; + } + + memcpy(recv_data_buffer.header, data, 4); + recv_data_buffer.frame_number = *(data + 4); + recv_data_buffer.command = *(data + 5); + recv_data_buffer.data_len = *(data + 6) | (*(data + 7) << 8); + + if (recv_data_buffer.data_len) { + memset(&recv_data_buffer.data[0], 0, sizeof(recv_data_buffer.data)); + memcpy(&recv_data_buffer.data[0], data + 8, recv_data_buffer.data_len); + } + + gamepad_data_handler(serdev, &recv_data_buffer); + return count; +} + +static const struct serdev_device_ops gamepad_mcu_uart_client_ops = { + .receive_buf = gamepad_mcu_uart_rx_bytes, +}; + +static int gamepad_mcu_uart_probe(struct serdev_device *serdev) +{ + struct device *dev = &serdev->dev; + struct gamepad_device *gamepad_dev; + int ret; + + gamepad_dev = devm_kzalloc(dev, sizeof(*gamepad_dev), GFP_KERNEL); + if (!gamepad_dev) { + dev_err(dev, "could not allocate memory for device data\n"); + return -ENOMEM; + } + + gamepad_dev->en_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH); + if (IS_ERR(gamepad_dev->en_gpio)) { + ret = PTR_ERR(gamepad_dev->en_gpio); + goto err_free_dev; + } + + ret = devm_serdev_device_open(dev, serdev); + if (ret) { + dev_err(dev, "Unable to open UART device"); + goto err_free_dev; + } + gamepad_dev->dev = dev; + + serdev_device_set_drvdata(serdev, gamepad_dev); + + ret = serdev_device_set_baudrate(serdev, 115200); + if (ret < 0) { + dev_err(dev, "Failed to set up host baud rate (%d)", ret); + goto err_free_dev; + } + + serdev_device_set_flow_control(serdev, false); + + gamepad_dev->dev_input = input_allocate_device(); + if (!gamepad_dev->dev_input) { + dev_err(dev, + "Not enough memory for input input device\n"); + ret = -ENOMEM; + goto err_free_dev; + } + + gamepad_dev->dev_input->name = "Ayn Odin2 Gamepad"; + gamepad_dev->dev_input->phys = "odin2-gamepad/input0"; + __set_bit(EV_ABS, gamepad_dev->dev_input->evbit); + + for (int i = 0; i < ARRAY_SIZE(keymap); i++) + input_set_capability(gamepad_dev->dev_input, EV_KEY, keymap[i]); + + input_set_capability(gamepad_dev->dev_input, EV_KEY, BTN_JOYSTICK); + + for (int i = ABS_X; i <= ABS_RZ; i++) + input_set_abs_params(gamepad_dev->dev_input, i, 0x50, 0xa50, 0, 0); + + input_set_abs_params(gamepad_dev->dev_input, ABS_HAT1X, 0, 0x750, 0, 30); + input_set_abs_params(gamepad_dev->dev_input, ABS_HAT1Y, 0, 0x750, 0, 30); + + ret = input_register_device(gamepad_dev->dev_input); + if (ret) { + dev_err(dev, "Could not register input device"); + goto err_free_dev; + } + + serdev_device_set_client_ops(serdev, &gamepad_mcu_uart_client_ops); + + gamepad_send_init_sequence(serdev); + + return 0; + +err_free_dev: + if (gamepad_dev->dev_input) { + input_free_device(gamepad_dev->dev_input); + } + + if (gamepad_dev) { + devm_kfree(dev, gamepad_dev); + } + return ret; +} + +static void gamepad_mcu_uart_remove(struct serdev_device *serdev) +{ + + return; +} + + +static const struct of_device_id gamepad_mcu_uart_of_match[] = { + { .compatible = "ayn,odin2-gamepad"}, + {} +}; +MODULE_DEVICE_TABLE(of, gamepad_mcu_uart_of_match); + +static struct serdev_device_driver gamepad_mcu_uart_driver = { + .driver = { + .name = "odin2-gamepad", + .of_match_table = gamepad_mcu_uart_of_match, + }, + .probe = gamepad_mcu_uart_probe, + .remove = gamepad_mcu_uart_remove, +}; + +module_serdev_device_driver(gamepad_mcu_uart_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Gamepad driver for Ayn Odin2"); +MODULE_AUTHOR("Molly Sophia "); \ No newline at end of file diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h index c23d5e41e25b..e563af5af4f4 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h @@ -18,6 +18,7 @@ #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158 #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184 @@ -27,5 +28,6 @@ #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8 #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4 #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220 #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h index f420f8faf16a..ef392ce21a8a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h @@ -56,6 +56,8 @@ #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4 #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8 #define QSERDES_V6_COM_PLL_IVCO 0xf4 +#define QSERDES_V6_COM_CMN_IETRIM 0xfc +#define QSERDES_V6_COM_CMN_IPTRIM 0x100 #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110 #define QSERDES_V6_COM_RESETSM_CNTRL 0x118 #define QSERDES_V6_COM_LOCK_CMP_EN 0x120 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h index 15bcb4ba9139..48f31c8327ff 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h @@ -10,10 +10,20 @@ #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34 +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10 +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24 +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54 +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4 +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0 +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4 #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178 +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214 @@ -25,6 +35,8 @@ #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264 #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270 #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280 +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284 #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8 #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 514fa14df634..d5ff809ff9c5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -754,32 +754,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c), +}; + +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44), +}; + +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), + + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), +}; + +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), + + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), }; static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05), QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), }; +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c), +}; + static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2), @@ -795,14 +814,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), }; +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), +}; + +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08), + + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30), +}; + static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69), QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), +}; + +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e), +}; + struct qmp_ufs_offsets { u16 serdes; u16 pcs; @@ -836,6 +887,8 @@ struct qmp_phy_cfg { const struct qmp_phy_cfg_tbls tbls_hs_b; /* Additional sequence for HS G4 */ const struct qmp_phy_cfg_tbls tbls_hs_g4; + /* Additional sequence for HS G4 */ + const struct qmp_phy_cfg_tbls tbls_hs_g5; /* clock ids to be requested */ const char * const *clk_list; @@ -1296,6 +1349,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { .pcs = sm8550_ufsphy_pcs, .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), }, + .tbls_hs_b = { + .serdes = sm8550_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), + }, + .tbls_hs_g4 = { + .serdes = sm8550_ufsphy_g4_serdes, + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes), + .tx = sm8550_ufsphy_g4_tx, + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx), + .rx = sm8550_ufsphy_g4_rx, + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx), + .pcs = sm8550_ufsphy_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs), + }, + .tbls_hs_g5 = { + .serdes = sm8550_ufsphy_g5_serdes, + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes), + .rx = sm8550_ufsphy_g5_rx, + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx), + .pcs = sm8550_ufsphy_g5_pcs, + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs), + }, .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -1361,14 +1436,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) { qmp_ufs_serdes_init(qmp, &cfg->tbls); + if (qmp->submode == UFS_HS_G4) + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4); + else if (qmp->submode == UFS_HS_G5) + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5); + if (qmp->mode == PHY_MODE_UFS_HS_B) qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b); + qmp_ufs_lanes_init(qmp, &cfg->tbls); if (qmp->submode == UFS_HS_G4) qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4); + else if (qmp->submode == UFS_HS_G5) + qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g5); + qmp_ufs_pcs_init(qmp, &cfg->tbls); if (qmp->submode == UFS_HS_G4) qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4); + else if (qmp->submode == UFS_HS_G5) + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g5); } static int qmp_ufs_com_init(struct qmp_ufs *qmp) diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 23074714a81a..95bee96e84a7 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_REGULATOR) += core.o dummy.o fixed-helper.o helpers.o devres.o irq_helpers.o obj-$(CONFIG_OF) += of_regulator.o obj-$(CONFIG_REGULATOR_FIXED_VOLTAGE) += fixed.o +obj-$(CONFIG_REGULATOR_FIXED_VOLTAGE) += wlan.o obj-$(CONFIG_REGULATOR_VIRTUAL_CONSUMER) += virtual.o obj-$(CONFIG_REGULATOR_USERSPACE_CONSUMER) += userspace-consumer.o diff --git a/drivers/regulator/wlan.c b/drivers/regulator/wlan.c new file mode 100644 index 000000000000..e988283d3a1e --- /dev/null +++ b/drivers/regulator/wlan.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct wlan_data { + struct regulator_desc desc; + struct regulator_dev *dev; + struct regulator **regulators; + unsigned int count; + struct gpio_desc *enable; + bool enabled; +}; + +static int regulator_wlan_enable(struct regulator_dev *rdev) +{ + struct wlan_data *priv = rdev_get_drvdata(rdev); + int ret, i; + + if (priv->enabled) + return 0; + + for (i = 0; i < priv->count; ++i) { + ret = regulator_enable(priv->regulators[i]); + if (ret < 0) { + return ret; + } + + msleep(20); + } + + gpiod_set_value(priv->enable, 1); + + msleep(200); + + priv->enabled = true; + + return 0; +} + +static int regulator_wlan_disable(struct regulator_dev *rdev) +{ + struct wlan_data *priv = rdev_get_drvdata(rdev); + int ret, i; + + if (!priv->enabled) + return 0; + + gpiod_set_value(priv->enable, 0); + + for (i = 0; i < priv->count; ++i) { + ret = regulator_disable(priv->regulators[i]); + if (ret < 0) + return ret; + } + + priv->enabled = false; + + return 0; +} + +static int regulator_wlan_is_enabled(struct regulator_dev *rdev) +{ + struct wlan_data *priv = rdev_get_drvdata(rdev); + + return priv->enabled; +} + +static const struct regulator_ops regulator_wlan_ops = { + .enable = regulator_wlan_enable, + .disable = regulator_wlan_disable, + .is_enabled = regulator_wlan_is_enabled, +}; + +static const struct of_device_id regulator_wlan_of_match[] = { + { .compatible = "regulator-wlan" }, + {}, +}; +MODULE_DEVICE_TABLE(of, regulator_wlan_of_match); + +static int regulator_wlan_probe(struct platform_device *pdev) +{ + struct regulator_config cfg = { }; + struct wlan_data *drvdata; + int ret, i; + u32 count; + + drvdata = devm_kzalloc(&pdev->dev, sizeof(struct wlan_data), + GFP_KERNEL); + if (drvdata == NULL) + return -ENOMEM; + + drvdata->enable = devm_gpiod_get(&pdev->dev, "enable", GPIOD_OUT_LOW); + if (IS_ERR(drvdata->enable)) + return dev_err_probe(&pdev->dev, PTR_ERR(drvdata->enable), + "Failed to obtain enable gpio\n"); + + ret = device_property_read_u32(&pdev->dev, "supply-count", &count); + if (ret < 0) + return ret; + if (count == 0) + return -EINVAL; + + drvdata->regulators = devm_kmalloc_array(&pdev->dev, sizeof(struct regulator *), + count, GFP_KERNEL); + + for (i = 0; i < count; ++i) { + char prop_name[16]; + snprintf(prop_name, 16, "vin%d", i); + drvdata->regulators[i] = devm_regulator_get(&pdev->dev, prop_name); + if (IS_ERR(drvdata->regulators[i])) + return dev_err_probe(&pdev->dev, PTR_ERR(drvdata->regulators[i]), + "Failed to obtain supply '%d'\n", i); + } + drvdata->count = count; + + drvdata->desc.name = devm_kstrdup(&pdev->dev, dev_name(&pdev->dev), GFP_KERNEL); + drvdata->desc.type = REGULATOR_VOLTAGE; + drvdata->desc.owner = THIS_MODULE; + drvdata->desc.ops = ®ulator_wlan_ops; + + cfg.dev = &pdev->dev; + cfg.init_data = of_get_regulator_init_data(&pdev->dev, pdev->dev.of_node, &drvdata->desc); + cfg.driver_data = drvdata; + cfg.of_node = pdev->dev.of_node; + + drvdata->dev = devm_regulator_register(&pdev->dev, &drvdata->desc, &cfg); + if (IS_ERR(drvdata->dev)) { + ret = dev_err_probe(&pdev->dev, PTR_ERR(drvdata->dev), + "Failed to register regulator: %ld\n", + PTR_ERR(drvdata->dev)); + return ret; + } + + platform_set_drvdata(pdev, drvdata); + + return 0; +} + +static struct platform_driver regulator_wlan_driver = { + .probe = regulator_wlan_probe, + .driver = { + .name = "wlan-regulator", + .of_match_table = of_match_ptr(regulator_wlan_of_match), + }, +}; + +module_platform_driver(regulator_wlan_driver); + +MODULE_DESCRIPTION("Wlan regulator"); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index b3634e10f6f5..763912688e7a 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -254,4 +254,17 @@ config QCOM_INLINE_CRYPTO_ENGINE tristate select QCOM_SCM +config QCOM_DUMP_XBL_LOG + tristate "Qualcomm driver to print XBL logs on console from debugfs" + help + This driver is used to capture secondary bootloader (xbl) log + from a reserved memory region and provide a debugfs entry to read + logs captured from this memory region and print them on console. + User can use below command to print the xbl log on console: + + cat /sys/kernel/debug/xbl_log + + These logs help to identify firmware configuration information on + the SoC. The name of the built module will be dump_xbl_log + endmenu diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index bbca2e1e55bb..aac088a1a0b6 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -32,3 +32,4 @@ obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o qcom_ice-objs += ice.o obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) += qcom_ice.o +obj-$(CONFIG_QCOM_DUMP_XBL_LOG) += dump_xbl_log.o diff --git a/drivers/soc/qcom/dump_xbl_log.c b/drivers/soc/qcom/dump_xbl_log.c new file mode 100644 index 000000000000..ea335a5e660b --- /dev/null +++ b/drivers/soc/qcom/dump_xbl_log.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct xbl_log_data { + struct device *dev; + size_t buf_size; + void __iomem *xbl_buf; + struct dentry *dbg_file; + struct debugfs_blob_wrapper dbg_data; +}; + +static int map_addr_range(struct device_node **parent, const char *name, + struct xbl_log_data *xbl_data) +{ + struct device_node *node; + struct resource res; + int ret; + + node = of_find_node_by_name(*parent, name); + if (!node) + return -ENODEV; + + ret = of_address_to_resource(node, 0, &res); + if (ret) { + dev_err(xbl_data->dev, "Failed to parse memory region\n"); + return ret; + } + of_node_put(node); + + if (!resource_size(&res)) { + dev_err(xbl_data->dev, "Failed to parse memory region size\n"); + return -ENODEV; + } + + xbl_data->buf_size = resource_size(&res) - 1; + xbl_data->xbl_buf = devm_memremap(xbl_data->dev, res.start, + xbl_data->buf_size, MEMREMAP_WB); + if (!xbl_data->xbl_buf) { + dev_err(xbl_data->dev, "%s: memory remap failed\n", name); + return -ENOMEM; + } + + return 0; +} + +static int xbl_log_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct xbl_log_data *xbl_data; + struct device_node *parent; + int ret; + + xbl_data = devm_kzalloc(dev, sizeof(*xbl_data), GFP_KERNEL); + if (!xbl_data) + return -ENOMEM; + + xbl_data->dev = &pdev->dev; + platform_set_drvdata(pdev, xbl_data); + + parent = of_find_node_by_path("/reserved-memory"); + if (!parent) { + dev_err(xbl_data->dev, "reserved-memory node missing\n"); + return -ENODEV; + } + + ret = map_addr_range(&parent, "uefi-log", xbl_data); + if (ret) + goto put_node; + + xbl_data->dbg_data.data = xbl_data->xbl_buf; + xbl_data->dbg_data.size = xbl_data->buf_size; + xbl_data->dbg_file = debugfs_create_blob("xbl_log", 0400, NULL, + &xbl_data->dbg_data); + if (IS_ERR(xbl_data->dbg_file)) { + dev_err(xbl_data->dev, "failed to create debugfs entry\n"); + ret = PTR_ERR(xbl_data->dbg_file); + } + +put_node: + of_node_put(parent); + return ret; +} + +static int xbl_log_remove(struct platform_device *pdev) +{ + struct xbl_log_data *xbl_data = platform_get_drvdata(pdev); + + debugfs_remove_recursive(xbl_data->dbg_file); + return 0; +} + +static struct platform_driver xbl_log_driver = { + .probe = xbl_log_probe, + .remove = xbl_log_remove, + .driver = { + .name = "xbl-log", + }, +}; + +static struct platform_device xbl_log_device = { + .name = "xbl-log", +}; + +static int __init xbl_log_init(void) +{ + int ret = 0; + + ret = platform_driver_register(&xbl_log_driver); + if (!ret) { + ret = platform_device_register(&xbl_log_device); + if (ret) + platform_driver_unregister(&xbl_log_driver); + } + return ret; +} + +static void __exit xbl_log_exit(void) +{ + platform_device_unregister(&xbl_log_device); + platform_driver_unregister(&xbl_log_driver); +} + +module_init(xbl_log_init); +module_exit(xbl_log_exit); + +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. (QTI) XBL log driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 96cb8b5b4e66..7c1d79985f23 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -442,7 +442,11 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct ufs_dev_params *host_pwr_cap = &host->host_pwr_cap; struct phy *phy = host->generic_phy; + enum phy_mode mode = host_pwr_cap->hs_rate == PA_HS_MODE_B ? + PHY_MODE_UFS_HS_B : + PHY_MODE_UFS_HS_A; int ret; /* Reset UFS Host Controller and PHY */ @@ -459,7 +463,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) return ret; } - phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear); + phy_set_mode_ext(phy, mode, host->phy_gear); /* power on phy - start serdes and phy's power and clocks */ ret = phy_power_on(phy); @@ -898,7 +902,6 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, struct ufs_pa_layer_attr *dev_req_params) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct ufs_dev_params ufs_qcom_cap; int ret = 0; if (!dev_req_params) { @@ -908,13 +911,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, switch (status) { case PRE_CHANGE: - ufshcd_init_pwr_dev_param(&ufs_qcom_cap); - ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE; - - /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ - ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba); - - ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap, + ret = ufshcd_get_pwr_dev_param(&host->host_pwr_cap, dev_max_params, dev_req_params); if (ret) { @@ -1047,10 +1044,43 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP); } - if (host->hw_ver.major > 0x3) + if (host->hw_ver.major > 0x3 && host->hw_ver.major < 0x5) hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; } +static void ufs_qcom_set_pwr_mode_limits(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct ufs_dev_params *host_pwr_cap = &host->host_pwr_cap; + u32 val, dev_major = 0; + + ufshcd_init_pwr_dev_param(host_pwr_cap); + + /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ + host_pwr_cap->hs_tx_gear = host_pwr_cap->hs_rx_gear = ufs_qcom_get_hs_gear(hba); + host->phy_gear = host_pwr_cap->hs_rx_gear; + + if (host->hw_ver.major < 0x5) { + /* + * Power up the PHY using the minimum supported gear (UFS_HS_G2). + * Switching to max gear will be performed during reinit if supported. + */ + host->phy_gear = UFS_HS_G2; + } else { + val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); + dev_major = FIELD_GET(GENMASK(7, 4), val); + + if (host->hw_ver.major == 0x5 && (dev_major >= 0x4 || + dev_major == 0)) { + /* For UFS 4.0 and newer, or dev version is not populated */ + host_pwr_cap->hs_rate = PA_HS_MODE_A; + } else if (dev_major < 0x4 && dev_major > 0) { + /* For UFS 3.1 and older, apply HS-G4 PHY settings to save power */ + host->phy_gear = UFS_HS_G4; + } + } +} + static void ufs_qcom_set_caps(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); @@ -1273,6 +1303,7 @@ static int ufs_qcom_init(struct ufs_hba *hba) if (err) goto out_variant_clear; + ufs_qcom_set_pwr_mode_limits(hba); ufs_qcom_set_caps(hba); ufs_qcom_advertise_quirks(hba); @@ -1292,12 +1323,6 @@ static int ufs_qcom_init(struct ufs_hba *hba) dev_warn(dev, "%s: failed to configure the testbus %d\n", __func__, err); - /* - * Power up the PHY using the minimum supported gear (UFS_HS_G2). - * Switching to max gear will be performed during reinit if supported. - */ - host->phy_gear = UFS_HS_G2; - return 0; out_variant_clear: diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 9950a0089475..6e02548699b7 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -56,6 +56,8 @@ enum { UFS_AH8_CFG = 0xFC, REG_UFS_CFG3 = 0x271C, + + REG_UFS_DEBUG_SPARE_CFG = 0x284C, }; /* QCOM UFS host controller vendor specific debug registers */ @@ -240,6 +242,7 @@ struct ufs_qcom_host { struct gpio_desc *device_reset; + struct ufs_dev_params host_pwr_cap; u32 phy_gear; bool esi_enabled;