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[SKiDL BUG]Paralel wires get overlayed #144
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This is to be expected since the routing done by |
@legalmachinery can you please explain how did you even get to this point? (installation steps, how did you get that ic to show up) i can't even get to outputting any schematic. All i get is this error:
Is it trying to access an attribute named: "x" in the pin class? i search through that class and i can't seem to find any variable with that name. should i put this on a separate bug report? thanks! OS Debian , Python 3.9, skidl-gensch latest |
Hi, paralel wires in my scheme appear to be overlayed as per the attached scheme. Is there any way to get them drawn separately please. Thank you.
OS Debian 10, Python 3.7, skidl latest.
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