Replies: 1 comment
-
The problem here is that you've specified SKIDL as the default tool and then tried to generate a netlist and XML file for that tool. But specific netlist and XML formats are associated with tools that have a way of processing those files to create other outputs such as a BOM or PCB layout (KiCad is an example of such a tool). SKiDL doesn't have anything like that so these functions don't exist and you get an error. (A more helpful error message should be produced when this happens.) In order to generate XML and netlist files, you should change the tool to KICAD before calling those functions. Or you could define file formats for SKiDL netlists and XML and then create the functions needed to generate those, but that seems like a lot of work. |
Beta Was this translation helpful? Give feedback.
-
Hello
I used Skidl with version 0.0.30 and Anaconda3.
The follow code is for save net and xml files.
from skidl import *
import io
set_default_tool(SKIDL)
v_in = Net('VIN')
print(v_in.name)
rup = Part("device_sklib.py", 'R', value='1K', footprint='Resistor_SMD.pretty:R_0805_2012Metric')
rlow = Part("device_sklib.py", 'R', value='500', footprint='Resistor_SMD.pretty:R_0805_2012Metric')
rup[1] += v_in
print(rup[1].net)
gnd = Net('GND')
rlow[1] += gnd
print(rlow[1].net)
v_in.do_erc = False
gnd.do_erc = False
ERC()
output = io.StringIO()
generate_netlist(file=output)
generate_xml(file=output)
And how to install the netlistsvg package for saving svg file?
Thank you for your help and response a lot.
Best-Regards
Jack
Beta Was this translation helpful? Give feedback.
All reactions