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vivado_1672.backup.log
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vivado_1672.backup.log
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#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Fri Jul 24 14:35:00 2020
# Process ID: 1672
# Current directory: D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent5836 D:\MSc_DSE\AUTUMN_TERM\Digital Design\Lab\Group project\Copy of Mem_subsyst_ full_interg\Mem_subsyst_ full_interg\Mem_subsyst_ full_interg.xpr
# Log file: D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/vivado.log
# Journal file: D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.xpr}
INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
Current project path is 'D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg'
INFO: [Project 1-313] Project file moved from 'E:/MSc DSE/AUTUMN TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg' since last save.
CRITICAL WARNING: [Project 1-311] Could not find the file 'D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.srcs/sources_1/imports/Digital Design/Parameterizable_ALU/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bits.vhd', nor could it be found using path 'E:/MSc DSE/AUTUMN TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.srcs/sources_1/imports/Digital Design/Parameterizable_ALU/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bits.vhd'.
CRITICAL WARNING: [Project 1-311] Could not find the file 'D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.srcs/sources_1/imports/Digital Design/Parameterizable_ALU/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd', nor could it be found using path 'E:/MSc DSE/AUTUMN TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.srcs/sources_1/imports/Digital Design/Parameterizable_ALU/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
open_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 822.652 ; gain = 107.090
update_compile_order -fileset sources_1
synth_design -rtl -name rtl_1
Command: synth_design -rtl -name rtl_1
Starting synth_design
Using part: xc7z020clg484-1
Top: Mem_Subsys_Full_Interg
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 927.730 ; gain = 96.316
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'Mem_Subsys_Full_Interg' [D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.srcs/sources_1/new/Mem_Subsys_Full_Interg.vhd:17]
Parameter data_size bound to: 16 - type: integer
Parameter reg_size bound to: 32 - type: integer
INFO: [Synth 8-638] synthesizing module 'control_logic' [D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.srcs/sources_1/imports/new/control_logic.vhd:52]
Parameter data_size bound to: 16 - type: integer
Parameter param_REG_size bound to: 32 - type: integer
ERROR: [Synth 8-5826] no such design unit 'reg_bits' in library 'work' [D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.srcs/sources_1/imports/new/control_logic.vhd:108]
ERROR: [Synth 8-285] failed synthesizing module 'control_logic' [D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.srcs/sources_1/imports/new/control_logic.vhd:52]
ERROR: [Synth 8-285] failed synthesizing module 'Mem_Subsys_Full_Interg' [D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.srcs/sources_1/new/Mem_Subsys_Full_Interg.vhd:17]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 947.164 ; gain = 115.750
---------------------------------------------------------------------------------
RTL Elaboration failed
2 Infos, 0 Warnings, 0 Critical Warnings and 4 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details
add_files -norecurse -scan_for_includes {{D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/REG_BANK/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bits.vhd} {D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/REG_BANK/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd}}
import_files -norecurse {{D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/REG_BANK/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bits.vhd} {D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/REG_BANK/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd}}
update_compile_order -fileset sources_1
import_files
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'constrs_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'constrs_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sim_1'
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'sources_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'
update_files -from_files {{D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/REG_BANK/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd}} -to_files {{D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.srcs/sources_1/imports/Digital Design/Parameterizable_ALU/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd}} -filesets [get_filesets *]
INFO: [filemgmt 20-762] Replacing file 'D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.srcs/sources_1/imports/Digital Design/Parameterizable_ALU/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd' with file 'D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/REG_BANK/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd'.
INFO: [filemgmt 20-1080] Importing file from 'D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/REG_BANK/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd' to 'D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.srcs/sources_1/imports/Digital Design/Parameterizable_ALU/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd'.
ERROR: [Common 17-680] Path length exceeds 260-Byte maximum allowed by Windows: D:/MSc_DSE/AUTUMN_TERM/Digital Design/Lab/Group project/Copy of Mem_subsyst_ full_interg/Mem_subsyst_ full_interg/Mem_subsyst_ full_interg.srcs/sources_1/imports/Digital Design/Parameterizable_ALU/parameterizable_register_bank/parameterizable_register_bank.srcs/sources_1/new/reg_bank.vhd
Please consider using the OS subst command to shorten the path length by mapping part of the path to a virtual drive letter. See Answer Record AR52787 for more information.
Resolution: In Windows 7 or later, the mklink command can also be used to create a symbolic link and shorten the path.
exit
INFO: [Common 17-206] Exiting Vivado at Fri Jul 24 14:40:13 2020...