Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

adjust timing between DRAM controller and last level cache #2

Open
MasWag opened this issue Sep 23, 2015 · 0 comments
Open

adjust timing between DRAM controller and last level cache #2

MasWag opened this issue Sep 23, 2015 · 0 comments

Comments

@MasWag
Copy link
Member

MasWag commented Sep 23, 2015

Now, the timing used in test of cache may be different from that of DRAM controller(zept is making). After zept finish writting it, cache's timing has to be adjusted.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@MasWag