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system.mhs
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system.mhs
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# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 12.1 Build EDK_MS1.53d
# Tue Jun 22 23:01:23 2010
# Target Board: Xilinx Virtex 4 ML405 Evaluation Platform Rev 1
# Family: virtex4
# Device: xc4vfx20
# Package: ff672
# Speed Grade: -10
# Processor number: 1
# Processor 1: ppc405_0
# Processor clock frequency: 300.0
# Bus clock frequency: 100.0
# Debug Interface: FPGA JTAG
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO_pin, DIR = IO, VEC = [0:3]
PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO_pin, DIR = IO, VEC = [0:4]
PORT fpga_0_Push_Buttons_Position_GPIO_IO_pin = fpga_0_Push_Buttons_Position_GPIO_IO_pin, DIR = IO, VEC = [0:4]
PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda_pin, DIR = IO
PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl_pin, DIR = IO
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin_vslice_6_1_concat, DIR = O, VEC = [6:1]
PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR = I
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR = I
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR = IO, VEC = [15:0]
PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr_pin, DIR = O, VEC = [1:0]
PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr_pin, DIR = O, VEC = [12:0]
PORT fpga_0_DDR_SDRAM_DDR_DQ_pin = fpga_0_DDR_SDRAM_DDR_DQ_pin, DIR = IO, VEC = [31:0]
PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM_pin, DIR = O, VEC = [3:0]
PORT fpga_0_DDR_SDRAM_DDR_DQS_pin = fpga_0_DDR_SDRAM_DDR_DQS_pin, DIR = IO, VEC = [3:0]
PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin, DIR = O
PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin, DIR = I
PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin, DIR = O, VEC = [7:0]
PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin, DIR = O
PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin, DIR = O
PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin, DIR = O
PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin, DIR = I, VEC = [7:0]
PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin, DIR = I
PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin, DIR = I
PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin, DIR = I
PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin = fpga_0_TriMode_MAC_GMII_MDC_0_pin, DIR = O
PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin = fpga_0_TriMode_MAC_GMII_MDIO_0_pin, DIR = IO
PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A_pin_vslice_9_29_concat, DIR = O, VEC = [9:29]
PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN_pin, DIR = O
PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN_pin, DIR = O
PORT fpga_0_FLASH_Mem_CE_pin = fpga_0_FLASH_Mem_CE_pin, DIR = O
PORT fpga_0_FLASH_Mem_DQ_pin = fpga_0_FLASH_Mem_DQ_pin, DIR = IO, VEC = [0:31]
PORT fpga_0_RS232_Uart_sin_pin = fpga_0_RS232_Uart_sin_pin, DIR = I
PORT fpga_0_RS232_Uart_sout_pin = fpga_0_RS232_Uart_sout_pin, DIR = O
PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
BEGIN ppc405_virtex4
PARAMETER INSTANCE = ppc405_0
PARAMETER C_IDCR_BASEADDR = 0b0100000000
PARAMETER HW_VER = 2.01.b
PARAMETER C_IPLB0_P2P = 0
PARAMETER C_DPLB0_P2P = 0
BUS_INTERFACE DPLB0 = plb
BUS_INTERFACE IPLB0 = plb
BUS_INTERFACE DPLB1 = ppc405_0_dplb1
BUS_INTERFACE IPLB1 = ppc405_0_iplb1
BUS_INTERFACE JTAGPPC = ppc405_0_jtagppc_bus
BUS_INTERFACE RESETPPC = ppc_reset_bus
PORT CPMC405CLOCK = clk_300_0000MHzDCM0
PORT EICC405EXTINPUTIRQ = ppc405_0_EICC405EXTINPUTIRQ
END
BEGIN plb_v46
PARAMETER INSTANCE = plb
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
PARAMETER HW_VER = 1.04.a
PORT PLB_Clk = clk_100_0000MHzDCM0
PORT SYS_Rst = sys_bus_reset
END
BEGIN xps_bram_if_cntlr
PARAMETER INSTANCE = xps_bram_if_cntlr_1
PARAMETER C_SPLB_NATIVE_DWIDTH = 64
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0xffff0000
PARAMETER C_HIGHADDR = 0xffffffff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END
BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END
BEGIN xps_gpio
PARAMETER INSTANCE = LEDs_4Bit
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81440000
PARAMETER C_HIGHADDR = 0x8144ffff
BUS_INTERFACE SPLB = plb
PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO_pin
END
BEGIN xps_gpio
PARAMETER INSTANCE = LEDs_Positions
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_GPIO_WIDTH = 5
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81420000
PARAMETER C_HIGHADDR = 0x8142ffff
BUS_INTERFACE SPLB = plb
PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO_pin
END
BEGIN xps_gpio
PARAMETER INSTANCE = Push_Buttons_Position
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_GPIO_WIDTH = 5
PARAMETER C_INTERRUPT_PRESENT = 1
PARAMETER C_IS_DUAL = 0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81400000
PARAMETER C_HIGHADDR = 0x8140ffff
BUS_INTERFACE SPLB = plb
PORT IP2INTC_Irpt = Push_Buttons_Position_IP2INTC_Irpt
PORT GPIO_IO = fpga_0_Push_Buttons_Position_GPIO_IO_pin
END
BEGIN xps_iic
PARAMETER INSTANCE = IIC_EEPROM
PARAMETER C_IIC_FREQ = 100000
PARAMETER C_TEN_BIT_ADR = 0
PARAMETER HW_VER = 2.03.a
PARAMETER C_BASEADDR = 0x81600000
PARAMETER C_HIGHADDR = 0x8160ffff
BUS_INTERFACE SPLB = plb
PORT IIC2INTC_Irpt = IIC_EEPROM_IIC2INTC_Irpt
PORT Sda = fpga_0_IIC_EEPROM_Sda_pin
PORT Scl = fpga_0_IIC_EEPROM_Scl_pin
END
BEGIN xps_sysace
PARAMETER INSTANCE = SysACE_CompactFlash
PARAMETER C_MEM_WIDTH = 16
PARAMETER HW_VER = 1.01.a
PARAMETER C_BASEADDR = 0x83600000
PARAMETER C_HIGHADDR = 0x8360ffff
BUS_INTERFACE SPLB = plb
PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin_vslice_6_1_concat & 0b0
PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin
PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin
PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin
PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin
END
BEGIN mpmc
PARAMETER INSTANCE = DDR_SDRAM
PARAMETER C_NUM_PORTS = 3
PARAMETER C_NUM_IDELAYCTRL = 2
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2
PARAMETER C_USE_MIG_V4_PHY = 1
PARAMETER C_MEM_TYPE = DDR
PARAMETER C_MEM_PARTNO = HYB25D512160BE-5
PARAMETER C_MEM_DATA_WIDTH = 32
PARAMETER C_PIM0_BASETYPE = 2
PARAMETER C_PIM1_BASETYPE = 2
PARAMETER C_PIM2_BASETYPE = 3
PARAMETER C_SDMA2_PI2LL_CLK_RATIO = 1
PARAMETER HW_VER = 6.00.a
PARAMETER C_MPMC_BASEADDR = 0x00000000
PARAMETER C_MPMC_HIGHADDR = 0x07FFFFFF
PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000
PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460FFFF
PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
BUS_INTERFACE SPLB0 = ppc405_0_iplb1
BUS_INTERFACE SPLB1 = ppc405_0_dplb1
BUS_INTERFACE SDMA_CTRL2 = plb
BUS_INTERFACE SDMA_LL2 = TriMode_MAC_GMII_LLINK0
PORT SDMA2_Clk = clk_100_0000MHzDCM0
PORT SDMA2_Rx_IntOut = DDR_SDRAM_SDMA2_Rx_IntOut
PORT SDMA2_Tx_IntOut = DDR_SDRAM_SDMA2_Tx_IntOut
PORT MPMC_Clk0 = clk_100_0000MHzDCM0
PORT MPMC_Clk90 = clk_100_0000MHz90DCM0
PORT MPMC_Clk_200MHz = clk_200_0000MHz
PORT MPMC_Rst = sys_periph_reset
PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk_pin
PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n_pin
PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE_pin
PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n_pin
PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n_pin
PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n_pin
PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n_pin
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr_pin
PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr_pin
PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ_pin
PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM_pin
PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS_pin
END
BEGIN plb_v46
PARAMETER INSTANCE = ppc405_0_iplb1
PARAMETER HW_VER = 1.04.a
PORT PLB_Clk = clk_100_0000MHzDCM0
PORT SYS_Rst = sys_bus_reset
END
BEGIN plb_v46
PARAMETER INSTANCE = ppc405_0_dplb1
PARAMETER HW_VER = 1.04.a
PORT PLB_Clk = clk_100_0000MHzDCM0
PORT SYS_Rst = sys_bus_reset
END
BEGIN mgt_protector
PARAMETER INSTANCE = MGT_wrapper
PARAMETER C_NUM_TILES = 4
PARAMETER C_USE_0 = 1
PARAMETER C_USE_1 = 1
PARAMETER C_USE_2 = 1
PARAMETER C_USE_3 = 1
PARAMETER C_LOC_0_AB = GT11_X0Y3-GT11_X0Y2
PARAMETER C_LOC_1_AB = GT11_X0Y1-GT11_X0Y0
PARAMETER C_LOC_2_AB = GT11_X1Y3-GT11_X1Y2
PARAMETER C_LOC_3_AB = GT11_X1Y1-GT11_X1Y0
PARAMETER HW_VER = 1.00.a
PORT CLK = clk_100_0000MHzDCM0
END
BEGIN xps_ll_temac
PARAMETER INSTANCE = TriMode_MAC_GMII
PARAMETER C_NUM_IDELAYCTRL = 4
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3
PARAMETER C_PHY_TYPE = 1
PARAMETER C_BUS2CORE_CLK_RATIO = 1
PARAMETER C_TEMAC_TYPE = 1
PARAMETER HW_VER = 2.03.a
PARAMETER C_BASEADDR = 0xffc00000
PARAMETER C_HIGHADDR = 0xffc7ffff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE LLINK0 = TriMode_MAC_GMII_LLINK0
PORT TemacIntc0_Irpt = TriMode_MAC_GMII_TemacIntc0_Irpt
PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin
PORT GTX_CLK_0 = clk_125_0000MHz
PORT REFCLK = clk_200_0000MHz
PORT LlinkTemac0_CLK = clk_100_0000MHzDCM0
PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin
PORT GMII_TXD_0 = fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin
PORT GMII_TX_EN_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin
PORT GMII_TX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin
PORT GMII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin
PORT GMII_RXD_0 = fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin
PORT GMII_RX_DV_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin
PORT GMII_RX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin
PORT GMII_RX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin
PORT MDC_0 = fpga_0_TriMode_MAC_GMII_MDC_0_pin
PORT MDIO_0 = fpga_0_TriMode_MAC_GMII_MDIO_0_pin
END
BEGIN xps_mch_emc
PARAMETER INSTANCE = FLASH
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_NUM_CHANNELS = 0
PARAMETER C_MEM0_WIDTH = 32
PARAMETER C_MAX_MEM_WIDTH = 32
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
PARAMETER C_SYNCH_MEM_0 = 0
PARAMETER C_TCEDV_PS_MEM_0 = 110000
PARAMETER C_TAVDV_PS_MEM_0 = 110000
PARAMETER C_THZCE_PS_MEM_0 = 10000
PARAMETER C_TWC_PS_MEM_0 = 55000
PARAMETER C_TWP_PS_MEM_0 = 55000
PARAMETER C_TLZWE_PS_MEM_0 = 35000
PARAMETER HW_VER = 3.01.a
PARAMETER C_MEM0_BASEADDR = 0xff000000
PARAMETER C_MEM0_HIGHADDR = 0xff7fffff
BUS_INTERFACE SPLB = plb
PORT RdClk = clk_100_0000MHzDCM0
PORT Mem_A = 0b000000000 & fpga_0_FLASH_Mem_A_pin_vslice_9_29_concat & 0b00
PORT Mem_OEN = fpga_0_FLASH_Mem_OEN_pin
PORT Mem_WEN = fpga_0_FLASH_Mem_WEN_pin
PORT Mem_CE = fpga_0_FLASH_Mem_CE_pin
PORT Mem_DQ = fpga_0_FLASH_Mem_DQ_pin
END
BEGIN xps_timebase_wdt
PARAMETER INSTANCE = xps_timebase_wdt_0
PARAMETER C_WDT_ENABLE_ONCE = 0
PARAMETER HW_VER = 1.01.a
PARAMETER C_BASEADDR = 0x83a00000
PARAMETER C_HIGHADDR = 0x83a0ffff
BUS_INTERFACE SPLB = plb
PORT Timebase_Interrupt = xps_timebase_wdt_0_Timebase_Interrupt
PORT WDT_Interrupt = xps_timebase_wdt_0_WDT_Interrupt
END
BEGIN xps_timer
PARAMETER INSTANCE = xps_timer_0
PARAMETER C_COUNT_WIDTH = 32
PARAMETER C_ONE_TIMER_ONLY = 0
PARAMETER HW_VER = 1.02.a
PARAMETER C_BASEADDR = 0x83c00000
PARAMETER C_HIGHADDR = 0x83c0ffff
BUS_INTERFACE SPLB = plb
PORT Interrupt = xps_timer_0_Interrupt
END
BEGIN xps_uart16550
PARAMETER INSTANCE = RS232_Uart
PARAMETER C_IS_A_16550 = 1
PARAMETER HW_VER = 3.00.a
PARAMETER C_BASEADDR = 0x83e00000
PARAMETER C_HIGHADDR = 0x83e0ffff
BUS_INTERFACE SPLB = plb
PORT sin = fpga_0_RS232_Uart_sin_pin
PORT sout = fpga_0_RS232_Uart_sout_pin
PORT IP2INTC_Irpt = RS232_Uart_IP2INTC_Irpt
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 100000000
PARAMETER C_CLKOUT0_PHASE = 90
PARAMETER C_CLKOUT0_GROUP = DCM0
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT1_FREQ = 100000000
PARAMETER C_CLKOUT1_PHASE = 0
PARAMETER C_CLKOUT1_GROUP = DCM0
PARAMETER C_CLKOUT1_BUF = TRUE
PARAMETER C_CLKOUT2_FREQ = 125000000
PARAMETER C_CLKOUT2_PHASE = 0
PARAMETER C_CLKOUT2_GROUP = NONE
PARAMETER C_CLKOUT2_BUF = TRUE
PARAMETER C_CLKOUT3_FREQ = 200000000
PARAMETER C_CLKOUT3_PHASE = 0
PARAMETER C_CLKOUT3_GROUP = NONE
PARAMETER C_CLKOUT3_BUF = TRUE
PARAMETER C_CLKOUT4_FREQ = 300000000
PARAMETER C_CLKOUT4_PHASE = 0
PARAMETER C_CLKOUT4_GROUP = DCM0
PARAMETER C_CLKOUT4_BUF = TRUE
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 4.00.a
PORT CLKIN = dcm_clk_s
PORT CLKOUT0 = clk_100_0000MHz90DCM0
PORT CLKOUT1 = clk_100_0000MHzDCM0
PORT CLKOUT2 = clk_125_0000MHz
PORT CLKOUT3 = clk_200_0000MHz
PORT CLKOUT4 = clk_300_0000MHzDCM0
PORT RST = sys_rst_s
PORT LOCKED = Dcm_all_locked
END
BEGIN jtagppc_cntlr
PARAMETER INSTANCE = jtagppc_cntlr_inst
PARAMETER HW_VER = 2.01.c
BUS_INTERFACE JTAGPPC0 = ppc405_0_jtagppc_bus
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 2.00.a
BUS_INTERFACE RESETPPC0 = ppc_reset_bus
PORT Slowest_sync_clk = clk_100_0000MHzDCM0
PORT Ext_Reset_In = sys_rst_s
PORT Dcm_locked = Dcm_all_locked
PORT Bus_Struct_Reset = sys_bus_reset
PORT Peripheral_Reset = sys_periph_reset
END
BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_BASEADDR = 0x81800000
PARAMETER C_HIGHADDR = 0x8180ffff
BUS_INTERFACE SPLB = plb
PORT Intr = Push_Buttons_Position_IP2INTC_Irpt & IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & TriMode_MAC_GMII_TemacIntc0_Irpt & xps_timebase_wdt_0_Timebase_Interrupt & xps_timebase_wdt_0_WDT_Interrupt & xps_timer_0_Interrupt & RS232_Uart_IP2INTC_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut & DDR_SDRAM_SDMA2_Tx_IntOut
PORT Irq = ppc405_0_EICC405EXTINPUTIRQ
END