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Selected names from 'unusual' places #249
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I didn't even know this existed in VHDL, but I find it amazing to help readability in code when you have for..generate and block. Would be cool to see this fixed! |
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VHDL allows to prefix a name with the label of the enclosing element as 'scope'. For example, for processes:
This example is directly taken from the LRM (8.3; examples)
At the moment, the language server sees this as an error.
The same is likely true for blocks, generate statements and probably more.
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