Analog IP design example: Sample and hold

This is a simple buffered sample and hold circuit demonstrating the use
of the CACE system.

Requires the CACE system to run testbenches:

	https://github.com/efabless/cace

Schematics for this amplifier are done in xschem and can be found in the
xschem/ directory.  Layouts for this amplifier are done in magic and can
be found in the mag/ directory.

The CACE specification is in cace/project.txt.  Testbench schematics are
in the cace/ directory.  Note that testbenches are editable in xschem,
and netlists can be generated, but netlists contain variables that must
be substituted by CACE and cannot simulate prior to variable substitution
by CACE.

To run cace in GUI mode:

	/path/to/cace_gui.py cace/sky130_ef_ip__samplehold.txt

CACE can also be run from the command line as:

	/path/to/cace.py cace/project.txt \
		cace/sky130_ef_ip__samplehold_out.txt \
		-source=schematic -param=<parameter_name> -summary"

Prerequisite design tools:

	xschem:  https://github.com/stefanschippers/xschem
	ngspice: git://git.code.sf.net/p/ngspice/ngspice
	magic:	 https://github.com/RTimothyEdwards/magic
	CACE:	 https://github.com/efabless/cace