Increment and decrement operators warning

[angelzzzzz]

Describe the bug
According to "IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language"11.4.2, the ordering of assignment operations relative to any other operation within an expression is undefined.

Therefore, it may require slang to be able to warn whenever a variable is both written and read-or-written within an integral expression or in other contexts where an implementation cannot guarantee order of evaluation.

For example:

i = 10;
j = i++ + (i = i - 1);

After execution, the value of j can be 18, 19, or 20 depending upon the relative ordering of the increment and the assignment statements.

To Reproduce
sv code:

module top();
    int i = 10;
    int j;
    initial begin
        j = i++ + (i = i - 1);
    end
endmodule

result:

pavo@Pavo:~/practice/sv$ slang test.sv
Top level design units:
    top

Build succeeded: 0 errors, 0 warnings