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squint.c
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squint.c
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/* Squint -- a peephole optimizer for mc.*/
/* mc.c uses a 2-register stack based VM. */
/* Squint converts this to a 2-register frame based VM. */
/* A 2-register frame based VM makes it easier to add */
/* a register allocation pass to the peephole optimizer. */
#include <stdio.h>
#include <stdlib.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h>
#include <string.h>
/* Register Use/Def Analysis
For each ARM instruction, create an integer descriptor describing
register usage. Since the stack simultaneously behaves like a
single register *and* an 'infinite' register file, we also need to
keep track of stack usage. We only track user-assignable registers
here, and (mostly) exclude the behavior of the fp, sp, lr, pc whose
behavior is constrained via both hardware and ABI conventions. We
do not track specific memory addresses, but do track use/def memOp.
Lower descriptor bits are used to mirror the Rn/Rd/Rs/Rm register
slots in an A32 opcode. This makes it easier to manipulate
'active' register slots in the actual instructions.
*/
/*
RI_memOp bits:
000 No memory operation
001 Inst read
010 Memory write
011 Memory read
100 Frame write
101 Frame read
110 Stack write
111 Stack read
*/
#define RI_hasD 0xc0000000 /* Destination register */
#define RI_RdDest 0x80000000 /* Rd destination register */
#define RI_RnDest 0x40000000 /* Rn destination register */
#define RI_memOp 0x38000000 /* Mem descriptor */
#define RI_memMask 0x30000000 /* Mem op mask */
#define RI_memRW 0x08000000 /* Read(1)/Write(0) op */
#define RI_instR 0x08000000 /* Instruction mem read */
#define RI_dataW 0x10000000 /* Rd written to memory */
#define RI_dataR 0x18000000 /* Rd read from memory */
#define RI_frameW 0x20000000 /* Rd written to frame var */
#define RI_frameR 0x28000000 /* Rd read from frame var */
#define RI_push 0x30000000 /* Rd is pushed onto stack */
#define RI_pop 0x38000000 /* Rd is popped off of stack */
#define RI_bb 0x04000000 /* basic block boundary */
#define RI_branch 0x02000000 /* branch instruction */
#define RI_FPacc 0x01000000 /* FP accumulate */
#define RI_func 0x00800000 /* function call */
#define RI_Sd 0x00400000 /* high bit of fp reg id */
#define RI_Sn 0x00200000 /* high bit of fp reg id */
#define RI_Sm 0x00100000 /* high bit of fp reg id */
#define RI_Active 0x000000f0 /* Bitmask for register usage in inst */
#define RI_RmAct 0x00000010
#define RI_RsAct 0x00000020
#define RI_RdAct 0x00000040
#define RI_RnAct 0x00000080
#define RI_Rm 0x0000000f /* register slots in ARM instruction */
#define RI_Rs 0x00000f00
#define RI_Rd 0x0000f000
#define RI_Rn 0x000f0000
/* NOP -- mov rn, rn */
#define NOP 0xe1a00000
#define NOP1 0xe1a01001
#define NOP11 0xe1a0b00b
#define NOP13 0xe1a0d00d
enum search_dir { S_BACK = -1, S_FWD = 1 };
struct ia_s {
int inst_addr; // inst address
struct ia_s *next;
};
static struct pd_s {
int data_addr; // data address
struct ia_s *inst;
} *cnst_pool;
static int cnst_pool_size;
static int *cbegin;
static int skip_const_blk;
/**********************************************************/
/*************** general utility functions ****************/
/**********************************************************/
static int popcount32b(int i)
{
i = i - ((i >> 1) & 0x55555555); // add pairs of bits
i = (i & 0x33333333) + ((i >> 2) & 0x33333333); // quads
i = (i + (i >> 4)) & 0x0F0F0F0F; // groups of 8
return (i * 0x01010101) >> 24; // horizontal sum of bytes
}
/**********************************************************/
/********** I-stream const pool utility functions ********/
/**********************************************************/
/* The ARM processor allows use of pc-relative constants */
/* constants are sorted by the address they are stored in memory */
static int find_const(int addr)
{
int low, high, mid;
// pool is sorted by *relative address* of data values
// with respect to beginning of text segment.
// binsearch pool for address of data
low = 0; high = cnst_pool_size;
while (low != high) {
mid = (low + high) / 2;
if (cnst_pool[mid].data_addr <= addr) {
low = mid;
if (cnst_pool[mid].data_addr == addr) break;
if (high-low == 1) ++low;
}
else
high = mid;
}
return low; // this is the inseertion point, which can be cnst_pool_size
}
static int is_const(int *inst)
{
if (cnst_pool_size == 0) return 0;
int addr = (inst-cbegin)*4;
return (cnst_pool[find_const(addr)].data_addr == addr);
}
/* pc-relative constants always appear in the instruction */
/* stream after the instructions that reference them. Because */
/* of this we can safely scan an instruction stream forward, */
/* skipping any constants we encounter. */
static void create_const_map(int *begin, int *end)
{
int *scan = begin;
int i;
/* initialize global variables */
cbegin = begin;
cnst_pool = calloc(end-begin, sizeof(struct pd_s)); // 1/4 prog size
cnst_pool_size = 0;
while (scan < end) {
if (!is_const(scan) &&
((i = (*scan & 0xffff0000) == 0xe59f0000) || // ldr r0, [pc, #X]
(*scan & 0xffbf0f00) == 0xed9f0a00)) { // vldr s0, [pc, #X]
int offset = i ? ((*scan & 0xfff) / 4) : (*scan & 0xff);
int addr = ((scan + 2 + offset) - begin)*4;
struct ia_s **inst;
int low = find_const(addr);
if (cnst_pool[low].data_addr != addr) {
int *mem = ((int *)&cnst_pool[cnst_pool_size]) + 1;
// insert addr at this location
for (i = cnst_pool_size; i > low; --i) {
*mem = *(mem-2); --mem;
*mem = *(mem-2); --mem;
}
cnst_pool[low].data_addr = addr;
cnst_pool[low].inst = 0;
++cnst_pool_size;
}
/* keep track of pc-relative instructions that ref this constant */
for (inst = &cnst_pool[low].inst; *inst != 0; inst = &(*inst)->next);
*inst = malloc(sizeof(struct ia_s));
(*inst)->inst_addr = (scan-begin)*4;
(*inst)->next = 0;
}
++scan;
}
}
static void delete_const(int *cnst, int *scan)
{
int addr = (scan-cbegin)*4;
int i = find_const((cnst-cbegin)*4);
struct ia_s *next, **inst = &cnst_pool[i].inst;
while (*inst && (*inst)->inst_addr != addr) inst = &(*inst)->next;
if (*inst) {
next = (*inst)->next;
(*inst)->next = 0;
free(*inst);
*inst = next;
}
if (cnst_pool[i].inst == 0) *cnst = NOP;
}
static void destroy_const_map()
{
struct ia_s *inst, *next;
int i;
for (i = 0; i < cnst_pool_size; ++i) {
inst = cnst_pool[i].inst;
while (inst != 0) {
next = inst->next;
free(inst);
inst = next;
}
}
free(cnst_pool);
}
/* convert special ARM consts to mov immediate */
static void const_imm_opt(int *begin, int *end)
{
struct ia_s *inst, *next;
int *newinst;
int i, j, val, rotate;
for (i = 0, j = 0; i < cnst_pool_size; ++i) {
val = cbegin[cnst_pool[i].data_addr/4];
rotate = 0;
if ((val & 0x0000ff00) && !(val & 0xffff00ff)) rotate = 1;
if ((val & 0x00ff0000) && !(val & 0xff00ffff)) rotate = 2;
if ((val & 0xff000000) && !(val & 0x00ffffff)) rotate = 3;
if (rotate || (-256 <= val && val < 0)) {
if (rotate) {
val = (val >> (8*rotate)) & 0xff;
rotate = (4-rotate)*1024;
}
inst = cnst_pool[i].inst;
while (inst != 0) {
next = inst->next;
newinst = cbegin + inst->inst_addr/4;
if ((*newinst & 0xffbf0f00) == 0xed9f0a00) goto skip_fp; // vldr
if (rotate) {
*newinst = 0xe3a00000 | (*newinst & RI_Rd) | rotate | val; // mov
}
else {
*newinst = 0xe3e00000 | (*newinst & RI_Rd) | -(val+1); // mvn
}
free(inst);
inst = next;
}
cbegin[cnst_pool[i].data_addr/4] = NOP; // for safety
}
else {
skip_fp: if (i != j) {
cnst_pool[j].data_addr = cnst_pool[i].data_addr;
cnst_pool[j].inst = cnst_pool[i].inst;
}
++j;
}
}
cnst_pool_size = j;
}
static void pack_const(int start)
{
int i, j;
for (i = start, j = start; i < cnst_pool_size; ++i) {
if (cnst_pool[i].inst != 0) {
if (i != j) {
cnst_pool[j].data_addr = cnst_pool[i].data_addr;
cnst_pool[j].inst = cnst_pool[i].inst;
}
++j;
}
}
cnst_pool_size = j;
return;
}
/* relocate a (v)ldr rX, [pc, #X] instruction */
static void rel_pc_ldr(int *dst, int *src)
{
if (dst == src) return;
int is_vldr = ((*src & 0xffbf0f00) == 0xed9f0a00); // vldr sd, [pc, #x]
if (is_vldr && ((src - dst + (*src & 0xff)) > 0xff)) {
printf("Squint can't relocate vldr -- out of range\n");
exit(-1);
}
struct ia_s **inst;
int offset = is_vldr ? (*src & 0xff) : ((*src & 0xfff) / 4);
int addr = ((src + 2 + offset) - cbegin)*4;
int low = find_const(addr);
if (cnst_pool[low].data_addr == addr) { // verify 'low' is index of const
for (inst = &cnst_pool[low].inst; *inst != 0; inst = &(*inst)->next) {
if ((*inst)->inst_addr == (src - cbegin)*4) {
/* make sure pc-relative addr is still valid after move */
(*inst)->inst_addr = (dst - cbegin)*4;
*dst = *src + (src - dst)*(is_vldr ? 1 : 4);
break;
}
}
}
}
/**********************************************************/
/************* NOP related utility functions **************/
/**********************************************************/
/* check for nop, PHD, and PHR0 instructions */
static int is_nop(int inst) {
return ( (inst == NOP) || (inst == NOP1) ||
(inst == NOP11) || (inst == NOP13) );
}
/* skip any nop instructions in given direction. */
/* direction: -1 means move toward lower addresses */
/* 1 means move toward higher addresses */
/* Note that a NOP1 (PHD) will treat the instruction */
/* after it (+1) as though it were a nop */
static int *skip_nop(int *begin, enum search_dir dir)
{ /* -1 = backward, 1 = forward */
int *scan2, *scan = begin;
int *after_const_block, done;
do {
done = 1;
/* skip past any consts in instruction stream */
while (is_const(scan)) scan += dir;
/* skip past any NOPS in instruction stream */
if (*scan == NOP || *scan == NOP11 || *scan == NOP13) {
scan += dir;
done = 0;
}
else if (dir == 1 &&
*scan == NOP1 &&
(*(scan+1) & 0xffff0fff) != 0xe52d0004) { /* push */
scan += 2;
done = 0;
}
else if (*(scan-1) == NOP1 &&
(*scan & 0xffff0fff) != 0xe52d0004 && /* push */
dir == -1) {
scan -= 2;
done = 0;
}
else if (*scan == NOP1) {
scan += dir;
done = 0;
}
else if (skip_const_blk && (*scan & 0xff800000) == 0xea000000) {
// expensive check but const-blocks have blocked many opts
after_const_block = scan + 2 + (*scan & 0x00ffffff);
for (scan2 = scan + 1; scan2 < after_const_block; ++scan2)
if (!is_const(scan2)) break;
if (scan2 == after_const_block) {
scan = ((dir == 1) ? after_const_block : (scan - 1));
done = 0;
}
}
} while (!done);
return scan;
}
/* This is a convenience function that should always */
/* start from a non-nop, non-const instruction. */
/* index is a count of how many non-nop instructions */
/* to move through the instruction stream. e.g. */
/* index == 0 means return immediately */
/* index == -5 means move backward 5 active instructions */
static int *active_inst(int *cursor, int index)
{
enum search_dir dir;
int count;
if (index != 0) {
if (index < 0) {
dir = S_BACK;
count = -index;
}
else {
dir = S_FWD;
count = index;
}
while (count > 0) {
cursor += dir;
cursor = skip_nop(cursor, dir);
--count;
}
}
return cursor;
}
/* This is executed immediately before compressing */
/* all nops out of the instruction stream */
static void rename_nop(int *begin, int *end)
{
int *scan;
for (scan = begin; scan <= end; ++scan) {
if (is_nop(*scan) && !is_const(scan)) {
*scan = NOP;
}
}
}
/****************************************************/
/****************** use-def analysis ****************/
/****************************************************/
/* The following bit masks are used to transfer 'active' register
slots between the def/use descriptors and the A32 opcodes.
*/
static int activeRegMask[16] =
{
0x00000000,
0x0000000f,
0x00000f00,
0x00000f0f,
0x0000f000,
0x0000f00f,
0x0000ff00,
0x0000ff0f,
0x000f0000,
0x000f000f,
0x000f0f00,
0x000f0f0f,
0x000ff000,
0x000ff00f,
0x000fff00,
0x000fff0f
};
/**********************************************/
#define NUM_USABLE_REG 11
static int regtest(int inst, int opmask)
{
return ((inst & opmask) == opmask);
}
/* funcBegin and funcEnd instructions guaranteed not to be NOP */
static void create_inst_info(int *instInfo, int *funcBegin, int *funcEnd)
{
int *scan;
int *rInfo = instInfo;
int Rn, Rd, Rs, Rm;
int inst, instMask, op;
for (scan = funcBegin; scan <= funcEnd; ++scan) {
int info = 0;
/* skip code that won't be transformed */
if (is_nop(*scan) && scan < funcEnd) {
int *end = skip_nop(scan, S_FWD);
if (end > funcEnd) end = funcEnd;
while (scan < end) {
if (*scan == NOP13) {
*rInfo++ = RI_func; // R0 set in func
}
else
*rInfo++ = info;
++scan;
}
}
/* determine info about current instruction */
inst = *scan;
instMask = (inst >> 24) & 0x0e;
Rn = (inst >> 16) & 0x0f;
Rd = (inst >> 12) & 0x0f;
Rs = (inst >> 8) & 0x0f;
Rm = inst & 0x0f;
if (instMask == 0x02) { /* ALU_immed */
op = (inst >> 21) & 0x0f;
if ((op != 0x0d) && (op != 0x0f)) {
info |= RI_RnAct;
}
if ((op & 0x0c) != 0x08) { // not tst instructions
info |= RI_RdAct | RI_RdDest;
}
}
else if (instMask == 0x00) { /* ALU_register */
if ((inst & 0xf0) == 0x90) { /* mul */
info |= RI_RnAct | RI_RsAct | RI_RmAct | RI_RnDest;
if (inst & (1<<21)) info |= RI_RdAct; // mla
}
else { /* not mul */
op = (inst >> 21) & 0x0f;
if ((op != 0x0d) && (op != 0x0f)) {
info |= RI_RnAct;
}
if ((op & 0x0c) != 0x08) {
info |= RI_RdAct | RI_RdDest;
}
if ((inst & 0x90) == 0x10) {
info |= RI_RsAct;
}
info |= RI_RmAct;
}
}
else if (instMask == 0x04 ||
(instMask == 0x06 && (inst & (1<<4)) == 0)) { /* MEM op */
int MEM_mask = (inst >> 20) & 0xd7;
if (MEM_mask == 0x51 || MEM_mask == 0x55) { /* ldr || ldrb */
info |= RI_RdAct | RI_RnAct | RI_RdDest;
if (inst & (1<<25)) {
info |= RI_RmAct;
}
if (Rn == 0x0f) {
info |= RI_instR;
}
else if (Rn == 0x0b) {
info |= RI_frameR;
}
else {
info |= RI_dataR;
}
if (Rd == 0x0f) {
info |= RI_branch;
}
}
else if (MEM_mask == 0x50 || MEM_mask == 0x54) { /* str | strb */
info |= RI_RdAct | RI_RnAct;
if (Rn == 0x0b) {
info |= RI_frameW;
}
else {
info |= RI_dataW;
}
}
else if (MEM_mask == 0x41) /* pop */
info |= RI_RdAct | RI_RnAct | RI_RdDest | RI_pop;
else if (MEM_mask == 0x52) /* push */
info |= RI_RdAct | RI_RnAct | RI_push;
}
else if (instMask == 0x0a) { /* BRANCH (and link) */
info |= RI_branch;
}
else if (instMask == 0x0c) { /* float */
if ((inst & 0xff200f00) == 0xed000a00) // vldr | vstr
info |= RI_RnAct;
if ((inst & 0xfff00f10) == 0xec500b10) // vmov rx, ry, dz
info |= RI_RnAct | RI_RdAct | RI_RnDest | RI_RdDest;
}
else if (instMask == 0x0e) { /* float */
if (((inst>>21) & 7) == 0 && // vmov sz, rx | (bit 20) vmov rx, sz
(inst & 0x10) == 0x10) {
info |= RI_RdAct | ((inst & (1<<20)) ? (RI_RdDest) : 0);
}
else if ((inst & 0xfff00f7f) == 0xee100a10) // fmrs
*rInfo = RI_RdAct | RI_RdDest;
else if ((inst & 0xfff00f7f) == 0xee000a10) // fmsr
*rInfo = RI_RdAct;
}
/* Mask out any registers outside of rename range */
if ( (Rn >= NUM_USABLE_REG) && regtest(info, RI_RnAct) ) {
info &= ~(RI_RnAct | RI_RnDest);
}
if ( (Rd >= NUM_USABLE_REG) && regtest(info, RI_RdAct) ) {
info &= ~(RI_RdAct | RI_RdDest);
if ((info & RI_memMask) == RI_push) { /* check for push or pop */
info &= ~RI_memOp; /* clear push/pop operation */
}
/* Note that RI_mem is left set here, since we still
need to handle pc relative addresses */
}
if ( (Rs >= NUM_USABLE_REG) && regtest(info, RI_RsAct) ) {
info &= ~RI_RsAct;
}
if ( (Rm >= NUM_USABLE_REG) && regtest(info, RI_RmAct) ) {
info &= ~RI_RmAct;
}
/* keep register Ids for active registers */
info |= inst & activeRegMask[(info & RI_Active) >> 4];
*rInfo++ = info;
}
/* termination sentinel to simplify reg_info scans */
*rInfo = 0xffffffff;
}
/* Floating point (hack) version of create_inst_info */
static void create_inst_info_f(int *instInfo, int *funcBegin, int *funcEnd)
{
int *scan;
int *rInfo = instInfo;
for (scan = funcBegin; scan <= funcEnd; ++scan) {
/* skip code that won't be transformed */
if (is_nop(*scan) && scan < funcEnd) {
int *end = skip_nop(scan, S_FWD);
if (end > funcEnd) end = funcEnd;
while (scan < end) {
if (*scan == NOP13) {
*rInfo++ = RI_func; // R0 set in func
}
else
*rInfo++ = 0; // not FP inst
++scan;
}
}
// order is important
if ((*scan & 0xffbf0fff) == 0xecbd0a01 || // vpop Fd
(*scan & 0xff300f00) == 0xed100a00) // vldr
*rInfo = RI_RdAct | RI_RdDest | ((*scan & 0x7000) * 2) |
((*scan & RI_Sd) >> 10) | ((*scan & 0x8000) << 7);
else if (*scan == 0xed2d0a01) // vpush s0
*rInfo = RI_RdAct;
else if ((*scan & 0xff300f00) == 0xed000a00) // vstr
*rInfo = RI_RdAct | ((*scan & 0x7000) * 2) |
((*scan & RI_Sd) >> 10) | ((*scan & 0x8000) << 7);
else if ((*scan & 0xffbf0fd0) == 0xeeb00a40) // vmov Fd, Fm
*rInfo = RI_RdAct | RI_RdDest | RI_RmAct | ((*scan & RI_Sd) >> 10) |
((*scan & 0x7000) * 2) | ((*scan & 0x8000) << 7) |
((*scan & 0x20) >> 5) | ((*scan & 0x07) * 2) |
((*scan & 0x08) << 17);
else if (*scan == 0xee300a40) // vsub s0, s0, s0
*rInfo = RI_RdAct | RI_RdDest; // def of s0, but not a use
else if ((*scan & 0xffbf0fff) == 0xeeb50ac0) // vcmpe Fd, #0
*rInfo = RI_RdAct | ((*scan & 0x7000) * 2) |
((*scan & RI_Sd) >> 10) | ((*scan & 0x8000) << 7);
else if ((*scan & 0xffbf0fd0) == 0xeeb40ac0) // vcmpe Fd, Fm
*rInfo = RI_RdAct | RI_RmAct | ((*scan & 0x7000) * 2) |
((*scan & RI_Sd) >> 10) | ((*scan & 0x8000) << 7) |
((*scan & 0x20) >> 5) | ((*scan & 0x07) * 2) |
((*scan & 0x08) << 17);
else if ((*scan & 0xffbf0fc0) == 0xeeb10ac0 || // vsqrt Fd, Fm
(*scan & 0xffbf0fc0) == 0xeeb10a40 || // vneg Fd, Fm
(*scan & 0xffbf0fc0) == 0xeeb00ac0) // vabs Fd, Fm
*rInfo = RI_RdAct | RI_RdDest | RI_RmAct | ((*scan & RI_Sd) >> 10) |
((*scan & 0x7000) * 2) | ((*scan & 0x8000) << 7) |
((*scan & 0x20) >> 5) | ((*scan & 0x07) * 2) |
((*scan & 0x08) << 17);
else if ((*scan & 0xffff0fd0) == 0xeeb70ac0) *rInfo = 0 ; // ignore
else if ((*scan & 0xfff00f7f) == 0xee100a10) // fmrs
*rInfo = RI_RnAct | ((*scan & 0x70000) * 2) |
((*scan & 0x80000) << 2) | ((*scan & 0x80) << 9);
else if ((*scan & 0xfff00f7f) == 0xee000a10) // fmsr
*rInfo = RI_RnAct | RI_RnDest | ((*scan & 0x70000) * 2) |
((*scan & 0x80000) << 2) | ((*scan & 0x80) << 9);
else if ((*scan & 0xffbf0fd0) == 0xeeb80ac0 || // fsitos
(*scan & 0xffbf0f50) == 0xeebd0a40) // ftosis
*rInfo = RI_RdAct | RI_RdDest | RI_RmAct | ((*scan & 0x20) >> 5) |
((*scan & 0x07) * 2) | ((*scan & 0x08) << 17) |
((*scan & RI_Sd) >> 10) | ((*scan & 0x7000) * 2) |
((*scan & 0x8000) << 7);
else if ((*scan & 0xff000f10) == 0xee000a00) { // Fop Fd, Fn, Fm
*rInfo = RI_RdAct | RI_RdDest | RI_RnAct | RI_RmAct |
((*scan & RI_Sd) >> 10) | ((*scan & 0x7000) * 2) |
((*scan & 0x8000) << 7) | ((*scan & 0x80) << 9) |
((*scan & 0x70000) * 2) | ((*scan & 0x80000) << 2) |
((*scan & 0x20) >> 5) | ((*scan & 0x07) * 2) |
((*scan & 0x08) << 17);
if ((*scan & 0x00b00000) == 0) *rInfo |= RI_FPacc;
}
else if ((*scan & 0x0e000000) == 0x0a000000)
*rInfo = RI_branch;
else
*rInfo = 0;
++rInfo;
}
/* termination sentinel to simplify reg_info scans */
*rInfo = 0xffffffff;
}
/* Mark block boundaries (after jump inst, or branch target inst) */
static void create_bb_info(int *instInfo, int *funcBegin, int *funcEnd)
{
int *scan, *dst;
for (scan = funcBegin; scan <= funcEnd; ++scan) {
if (instInfo[scan-funcBegin] & RI_branch) {
if (((*scan >> 24) & 0x0f) == 0x0a) { // not a pc load
if (((*scan >> 28) & 0x0f) < 0x0e) { // conditional branch
// mark fall-through instruction
dst = skip_nop(scan+1, S_FWD);
instInfo[dst-funcBegin] |= RI_bb;
}
// ignore const blocks, but mark other branch destinations.
// Note: const blocks act as NOP instructions for dep analysis.
if (scan == skip_nop(scan, S_FWD)) {
// mark jump destination instruction
int tmp = (*scan & 0x00ffffff) |
((*scan & 0x00800000) ? 0xff000000 : 0);
dst = skip_nop(scan + 2 + tmp, S_FWD);
instInfo[dst-funcBegin] |= RI_bb;
}
}
}
}
}
/* find first def of reg in given direction */
static int *find_def(int *instInfo, int *rInfo, int reg, enum search_dir dir)
{
int *retVal = 0;
int info;
while( (rInfo > instInfo) &&
*rInfo != 0xffffffff ) { /* if in-bounds of func */
info = *rInfo;
if (info & RI_hasD) {
int cmpReg = (info & RI_RnDest) ?
(((info & RI_Rn)>>16) | ((info & RI_Sn)>>17)) :
(((info & RI_Rd)>>12) | ((info & RI_Sd)>>18));
if (reg == cmpReg) {
retVal = rInfo;
break;
}
}
else if ((info & RI_func) && reg == 0) {
retVal = rInfo; // only good for location, not content
break;
}
rInfo += dir;
}
return retVal;
}
/* find first use of reg in given direction */
static int *find_use(int *instInfo, int *rInfo, int reg, enum search_dir dir)
{
int *retVal = 0;
int info;
while( (rInfo > instInfo) &&
*rInfo != 0xffffffff ) { /* if in-bounds of func */
info = *rInfo;
if (info & RI_hasD) {
// if not a memory op or a memory read, disable dest reg
if ((info & (RI_memOp | RI_FPacc)) == 0 || (info & RI_memRW)) {
info ^= (info & RI_RnDest) ? RI_RnAct : RI_RdAct;
}
}
if ((info & RI_RmAct) &&
((info & RI_Rm) | ((info & RI_Sm)>>16)) == reg) {
retVal = rInfo;
break;
}
if (info & RI_RsAct && ((info & RI_Rs)>>8) == reg) {
retVal = rInfo;
break;
}
if (info & RI_RdAct &&
(((info & RI_Rd)>>12) | ((info & RI_Sd)>>18)) == reg) {
retVal = rInfo;
break;
}
if (info & RI_RnAct &&
(((info & RI_Rn)>>16) | ((info & RI_Sn)>>17)) == reg) {
retVal = rInfo;
break;
}
rInfo += dir;
}
return retVal;
}
/* pass in valid use and def pointer */
static int *find_use_precede_def(int *instInfo, int *use, int *def,
int reg, enum search_dir dir)
{
int *finalUse = use;
if (def != 0) {
do {
finalUse = use;
use = find_use(instInfo, use + dir, reg, dir);
} while ( use != 0 && use < def);
}
if (use == def) finalUse = def;
return finalUse;
}
static void reg_rename(int newreg, int oldreg, int *use, int *inst)
{
int regSet = 0;
int mask = (*use & RI_Active);
if ((*use & RI_hasD) /* && !(*use & RI_FPacc) */) // don't overwite dest reg
mask &= ~((*use & RI_RdDest) ? RI_RdAct : RI_RnAct);
if ((mask & RI_RmAct) && (*inst & RI_Rm) == oldreg)
regSet |= newreg;
else
mask &= ~RI_RmAct;
if ((mask & RI_RsAct) && ((*inst & RI_Rs) >> 8) == oldreg)
regSet |= (newreg << 8);
else
mask &= ~RI_RsAct;
if ((mask & RI_RdAct) && ((*inst & RI_Rd) >> 12) == oldreg)
regSet |= (newreg << 12);
else
mask &= ~RI_RdAct;
if ((mask & RI_RnAct) && ((*inst & RI_Rn) >> 16) == oldreg)
regSet |= (newreg << 16);
else
mask &= ~RI_RnAct;
if (mask & RI_Active) { // rename registers
*inst = (*inst & ~activeRegMask[mask >> 4]) | regSet;
*use = (*use & ~activeRegMask[mask >> 4]) | regSet;
}
}
static void reg_rename_f(int newreg, int oldreg, int *use, int *inst)
{
int regSet = 0;
int mask = (*use & RI_Active);
if (*use & RI_hasD) // don't overwite dest reg
mask &= ~RI_RdAct;
if ((mask & RI_RmAct) &&
((*use & RI_Rm) | ((*use & RI_Sm) >> 16)) == oldreg)
regSet |= ((newreg & 0x0f) | ((newreg & 0x10) << 16));
else
mask &= ~RI_RmAct;
if ((mask & RI_RdAct) &&
(((*use & RI_Rd) >> 12) | ((*use & RI_Sd) >> 18)) == oldreg)
regSet |= (((newreg & 0x0f) << 12) | ((newreg & 0x10) << 18));
else
mask &= ~RI_RdAct;
if ((mask & RI_RnAct) &&
(((*use & RI_Rn) >> 16) | ((*use & RI_Sn) >> 17)) == oldreg)
regSet |= (((newreg & 0x0f) << 16) | ((newreg & 0x10) << 17));
else
mask &= ~RI_RnAct;
if (mask & RI_Active) { // rename registers
int tmp = *inst;
if (mask & RI_RdAct) {
tmp = (tmp & ~(RI_Rd | RI_Sd)) |
((newreg & 0x1e) << 11) | ((newreg & 1) << 22);
}
if (mask & RI_RnAct) {
tmp = (tmp & ~(RI_Rn | 0x80)) |
((newreg & 0x1e) << 15) | ((newreg & 1) << 7);
}
if (mask & RI_RmAct) {
tmp = (tmp & ~(RI_Rm | 0x20)) |
((newreg & 0x1e)>>1) | ((newreg & 1) << 5);
}
*inst = tmp;
*use = (*use & ~activeRegMask[mask >> 4]) | regSet;
}
}
/**********************************************************/
/********** peephole optimization funcs *******************/
/**********************************************************/
static void apply_peepholes1(int *funcBegin, int *funcEnd)
{
int *scan, *scanp1, *scanp2, *scanp3, off;
for (scan = funcBegin; scan < funcEnd; ++scan) {
scan = skip_nop(scan, S_FWD);
/* one instruction peepholes */
if (*scan == 0xe2400000 || /* sub r0, r0, #0 */
*scan == 0xe2800000) { /* add r0, r0, #0 */
*scan = NOP;
}
else { /* two instruction peephole */
scanp1 = active_inst(scan, 1);
if ((*scan & 0xfff00f00) == 0xe2800000 || // add rI, rS, #X
(*scan & 0xfff00f00) == 0xe2400000) { // sub rI, rS, #X
int rS = (*scan & RI_Rn) >> 16; // Source, RI_Rn
int rI = (*scan & RI_Rd) >> 12; // Index, RI_Rd
if ((*scanp1 & 0xff300000) == 0xe5100000 &&
((*scanp1 & RI_Rn) >> 16) == rI &&
(*scanp1 & RI_Rn) < (NUM_USABLE_REG<<16)) { // ldr[b] rX, [rI]
off = (*scanp1 & 0xfff) * ((*scanp1 & (1<<23)) ? 1 : -1);
off += (*scan & 0xff) *
(((*scan & 0xfff00000) == 0xe2800000) ? 1 : -1);
if (off < -4095 || off > 4095) continue;
*scanp1 = (*scanp1 & 0xff70f000) |
((off >= 0) ? (off | (1<<23)) : -off) |
(rS << 16); // ldr[b] rX, [rS, #X]
*scan = NOP;
}
else if ((*scanp1 & 0xff7fff00) == 0xed100a00) { // vldr s0,[r0,#X]
off = (*scanp1 & 0xff) * ((*scanp1 & (1<<23)) ? 1 : -1);
off += ((*scan & 0xff) / 4) *
(((*scan & 0xfff00000) == 0xe2800000) ? 1 : -1);
if (off < -255 || off > 255) continue;
*scanp1 = (*scanp1 & 0xff70ff00) |
((off >= 0) ? (off | (1<<23)) : -off) |
(rS << 16); // vldr s0, [rS, #X]
*scan = NOP;
}
}
}
}
funcEnd -= 2;
for (scan = funcBegin; scan < funcEnd; ++scan) {
scan = skip_nop(scan, S_FWD);
scanp1 = active_inst(scan, 1);
scanp2 = active_inst(scanp1, 1);
/* change register to immediate if possible */
if (*scan == 0xe52d0004 && /* push {r0} */
*scanp2 == 0xe49d1004 && /* pop {r1} */
(*scanp1 & 0xfffff000) == 0xe3a00000) { /* mov r0, #X */
scanp3 = active_inst(scanp2, 1);
if ((*scanp3 & 0xfe1fffff) == 0xe0010000 &&
(*scanp3>>23 & 0x3) != 0x2) { /* exclude comparisons */
*scanp3 = (*scanp3 ^ 1<<16) | 1<<25 | (*scanp1 & 0xfff);
*scan = NOP;
*scanp1 = NOP;
*scanp2 = NOP;
scan = scanp3;
}
else if (*scanp3 == 0xe1a00051 || /* asr r0, r1, r0 */
*scanp3 == 0xe1a00011) { /* lsl r0, r1, r0 */
int shift = ((*scanp1 & 0xff) < 0x20) ? (*scanp1 & 0x1f) : 0x1f;
*scanp3 = (*scanp3 & 0xffffffe0) | (shift << 7);
*scan = NOP;
*scanp1 = NOP;
*scanp2 = NOP;
scan = scanp3;
}
}
else if ((*scan & 0xffffff00) == 0xe3a00000 && (*scan & 0xff) &&
*scanp1 == 0xe3500000 && ((*scanp2 >> 24) & 0xff) == 0x1a) {
*scan = NOP; *scanp1 = NOP;
*scanp2 = 0xea000000 | (*scanp2 & 0x00ffffff);
scan = scanp2;
}
}
funcEnd += 2;
}
static void apply_peepholes2(int *instInfo, int *funcBegin, int *funcEnd)
{
int *scan;
int *scanp1, *scanp2, *scanp3, *scanp4, *scanp5;
int *scanm1, *scanm2;
create_inst_info(instInfo, funcBegin, funcEnd);
funcEnd -= 6;
for (scan = funcBegin; scan < funcEnd; ++scan) {
scan = skip_nop(scan, S_FWD);
/* Convert array addressing to more compact form */
if ((*scan & 0xffffff00) == 0xe3a00000) { /* mov r0, #X */
int imm = *scan & 0xff;
scanm1 = active_inst(scan, -1);
scanp1 = active_inst(scan, 1);
if ((imm & (imm-1)) == 0 && // power of 2
*scanm1 == 0xe52d0004 && /* push {r0} */
*scanp1 == 0xe49d1004) { /* pop {r1} */
int *loc;
scanm2 = active_inst(scanm1, -1);
scanp2 = active_inst(scanp1, 1);
scanp3 = active_inst(scanp2, 1);
scanp4 = active_inst(scanp3, 1);
loc = &instInfo[scanm2-funcBegin];
if (find_def(instInfo, loc, 0, S_FWD) == loc &&
*scanp2 == 0xe0000091 && // mul r0, r1, r0
*scanp3 == 0xe49d1004 && // pop {r1}
*scanp4 == 0xe0810000) { // add r0, r1, r0
int lev=1;