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ARM.CMSIS.pdsc
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<?xml version="1.0" encoding="UTF-8"?>
<package schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">
<name>CMSIS</name>
<description>CMSIS (Cortex Microcontroller Software Interface Standard)</description>
<vendor>ARM</vendor>
<!-- <license>license.txt</license> -->
<url>http://www.keil.com/pack/</url>
<releases>
<release version="5.4.0" date="2018-08-01">
Aligned pack structure with repository.
The following folders are deprecated:
- CMSIS/Include/
- CMSIS/DSP_Lib/
CMSIS-Core(M): 5.1.2 (see revision history for details)
- Added Cortex-M1 support (beta).
CMSIS-Core(A): 1.1.2 (see revision history for details)
CMSIS-NN: 1.1.0
- Added new math functions.
CMSIS-RTOS2:
- API 2.1.3 (see revision history for details)
- RTX 5.4.0 (see revision history for details)
* Updated exception handling on Cortex-A
CMSIS-Driver:
- Flash Driver API V2.2.0
Utilities:
- SVDConv 3.3.21
- PackChk 1.3.71
</release>
<release version="5.3.0" date="2018-02-22">
Updated Arm company brand.
CMSIS-Core(M): 5.1.1 (see revision history for details)
CMSIS-Core(A): 1.1.1 (see revision history for details)
CMSIS-DAP: 2.0.0 (see revision history for details)
CMSIS-NN: 1.0.0
- Initial contribution of the bare metal Neural Network Library.
CMSIS-RTOS2:
- RTX 5.3.0 (see revision history for details)
- OS Tick API 1.0.1
</release>
<release version="5.2.0" date="2017-11-16">
CMSIS-Core(M): 5.1.0 (see revision history for details)
- Added MPU Functions for ARMv8-M for Cortex-M23/M33.
- Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler.
CMSIS-Core(A): 1.1.0 (see revision history for details)
- Added compiler_iccarm.h.
- Added additional access functions for physical timer.
CMSIS-DAP: 1.2.0 (see revision history for details)
CMSIS-DSP: 1.5.2 (see revision history for details)
CMSIS-Driver: 2.6.0 (see revision history for details)
- CAN Driver API V1.2.0
- NAND Driver API V2.3.0
CMSIS-RTOS:
- RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata.
CMSIS-RTOS2:
- API 2.1.2 (see revision history for details)
- RTX 5.2.3 (see revision history for details)
Devices:
- Added GCC startup and linker script for Cortex-A9.
- Added device ARMCM0plus_MPU for Cortex-M0+ with MPU.
- Added IAR startup code for Cortex-A9
</release>
<release version="5.1.1" date="2017-09-19">
CMSIS-RTOS2:
- RTX 5.2.1 (see revision history for details)
</release>
<release version="5.1.0" date="2017-08-04">
CMSIS-Core(M): 5.0.2 (see revision history for details)
- Changed Version Control macros to be core agnostic.
- Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7.
CMSIS-Core(A): 1.0.0 (see revision history for details)
- Initial release
- IRQ Controller API 1.0.0
CMSIS-Driver: 2.05 (see revision history for details)
- All typedefs related to status have been made volatile.
CMSIS-RTOS2:
- API 2.1.1 (see revision history for details)
- RTX 5.2.0 (see revision history for details)
- OS Tick API 1.0.0
CMSIS-DSP: 1.5.2 (see revision history for details)
- Fixed GNU Compiler specific diagnostics.
CMSIS-Pack: 1.5.0 (see revision history for details)
- added System Description File (*.SDF) Format
CMSIS-Zone: 0.0.1 (Preview)
- Initial specification draft
</release>
<release version="5.0.1" date="2017-02-03">
Package Description:
- added taxonomy for Cclass RTOS
CMSIS-RTOS2:
- API 2.1 (see revision history for details)
- RTX 5.1.0 (see revision history for details)
CMSIS-Core: 5.0.1 (see revision history for details)
- Added __PACKED_STRUCT macro
- Added uVisior support
- Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__
- Updated template for secure main function (main_s.c)
- Updated template for Context Management for ARMv8-M TrustZone (tz_context.c)
CMSIS-DSP: 1.5.1 (see revision history for details)
- added ARMv8M DSP libraries.
CMSIS-Pack:1.4.9 (see revision history for details)
- added Pack Index File specification and schema file
</release>
<release version="5.0.0" date="2016-11-11">
Changed open source license to Apache 2.0
CMSIS_Core:
- Added support for Cortex-M23 and Cortex-M33.
- Added ARMv8-M device configurations for mainline and baseline.
- Added CMSE support and thread context management for TrustZone for ARMv8-M
- Added cmsis_compiler.h to unify compiler behaviour.
- Updated function SCB_EnableICache (for Cortex-M7).
- Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType
CMSIS-RTOS:
- bug fix in RTX 4.82 (see revision history for details)
CMSIS-RTOS2:
- new API including compatibility layer to CMSIS-RTOS
- reference implementation based on RTX5
- supports all Cortex-M variants including TrustZone for ARMv8-M
CMSIS-SVD:
- reworked SVD format documentation
- removed SVD file database documentation as SVD files are distributed in packs
- updated SVDConv for Win32 and Linux
CMSIS-DSP:
- Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.
- Added DSP libraries build projects to CMSIS pack.
</release>
<release version="4.5.0" date="2015-10-28">
- CMSIS-Core 4.30.0 (see revision history for details)
- CMSIS-DAP 1.1.0 (unchanged)
- CMSIS-Driver 2.04.0 (see revision history for details)
- CMSIS-DSP 1.4.7 (no source code change [still labeled 1.4.5], see revision history for details)
- CMSIS-Pack 1.4.1 (see revision history for details)
- CMSIS-RTOS 4.80.0 Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details)
- CMSIS-SVD 1.3.1 (see revision history for details)
</release>
<release version="4.4.0" date="2015-09-11">
- CMSIS-Core 4.20 (see revision history for details)
- CMSIS-DSP 1.4.6 (no source code change [still labeled 1.4.5], see revision history for details)
- CMSIS-Pack 1.4.0 (adding memory attributes, algorithm style)
- CMSIS-Driver 2.03.0 (adding CAN [Controller Area Network] API)
- CMSIS-RTOS
-- API 1.02 (unchanged)
-- RTX 4.79 (see revision history for details)
- CMSIS-SVD 1.3.0 (see revision history for details)
- CMSIS-DAP 1.1.0 (extended with SWO support)
</release>
<release version="4.3.0" date="2015-03-20">
- CMSIS-Core 4.10 (Cortex-M7 extended Cache Maintenance functions)
- CMSIS-DSP 1.4.5 (see revision history for details)
- CMSIS-Driver 2.02 (adding SAI (Serial Audio Interface) API)
- CMSIS-Pack 1.3.3 (Semantic Versioning, Generator extensions)
- CMSIS-RTOS
-- API 1.02 (unchanged)
-- RTX 4.78 (see revision history for details)
- CMSIS-SVD 1.2 (unchanged)
</release>
<release version="4.2.0" date="2014-09-24">
Adding Cortex-M7 support
- CMSIS-Core 4.00 (Cortex-M7 support, corrected C++ include guards in core header files)
- CMSIS-DSP 1.4.4 (Cortex-M7 support and corrected out of bound issues)
- CMSIS-Pack 1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial)
- CMSIS-SVD 1.2 (Cortex-M7 extensions)
- CMSIS-RTOS RTX 4.75 (see revision history for details)
</release>
<release version="4.1.1" date="2014-06-30">
- fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices
</release>
<release version="4.1.0" date="2014-06-12">
- CMSIS-Driver 2.02 (incompatible update)
- CMSIS-Pack 1.3 (see revision history for details)
- CMSIS-DSP 1.4.2 (unchanged)
- CMSIS-Core 3.30 (unchanged)
- CMSIS-RTOS RTX 4.74 (unchanged)
- CMSIS-RTOS API 1.02 (unchanged)
- CMSIS-SVD 1.10 (unchanged)
PACK:
- removed G++ specific files from PACK
- added Component Startup variant "C Startup"
- added Pack Checking Utility
- updated conditions to reflect tool-chain dependency
- added Taxonomy for Graphics
- updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers"
</release>
<release version="4.0.0">
- CMSIS-Driver 2.00 Preliminary (incompatible update)
- CMSIS-Pack 1.1 Preliminary
- CMSIS-DSP 1.4.2 (see revision history for details)
- CMSIS-Core 3.30 (see revision history for details)
- CMSIS-RTOS RTX 4.74 (see revision history for details)
- CMSIS-RTOS API 1.02 (unchanged)
- CMSIS-SVD 1.10 (unchanged)
</release>
<release version="3.20.4">
- CMSIS-RTOS 4.74 (see revision history for details)
- PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1.
</release>
<release version="3.20.3">
- CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change)
- CMSIS-RTOS 4.73 (see revision history for details)
</release>
<release version="3.20.2">
- CMSIS-Pack documentation has been added
- CMSIS-Drivers header and documentation have been added to PACK
- CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
</release>
<release version="3.20.1">
- CMSIS-RTOS Keil RTX V4.72 has been added to PACK
- CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
</release>
<release version="3.20.0">
The software portions that are deployed in the application program are now under a BSD license which allows usage
of CMSIS components in any commercial or open source projects. The Pack Description file Arm.CMSIS.pdsc describes the use cases
The individual components have been update as listed below:
- CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections.
- CMSIS-DSP library is optimized for more performance and contains several bug fixes.
- CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface.
- CMSIS-SVD is unchanged.
</release>
</releases>
<taxonomy>
<description Cclass="Board Support">Generic Interfaces for Evaluation and Development Boards</description>
<description Cclass="CMSIS" doc="CMSIS/Documentation/General/html/index.html">Cortex Microcontroller Software Interface Components</description>
<description Cclass="Device" doc="CMSIS/Documentation/Core/html/index.html">Startup, System Setup</description>
<description Cclass="CMSIS Driver" doc="CMSIS/Documentation/Driver/html/index.html">Unified Device Drivers compliant to CMSIS-Driver Specifications</description>
<description Cclass="File System">File Drive Support and File System</description>
<description Cclass="Graphics">Graphical User Interface</description>
<description Cclass="Network">Network Stack using Internet Protocols</description>
<description Cclass="USB">Universal Serial Bus Stack</description>
<description Cclass="Compiler">Compiler Software Extensions</description>
<description Cclass="RTOS">Real-time Operating System</description>
</taxonomy>
<devices>
<!-- ****************************** Cortex-M0 ****************************** -->
<family Dfamily="ARM Cortex M0" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M0 Device Generic Users Guide"/>
<description>
The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
- upward compatibility with the rest of the Cortex-M processor family.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM0">
<processor Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM0/Include/ARMCM0.h" define="ARMCM0"/>
</device>
</family>
<!-- ****************************** Cortex-M0P ****************************** -->
<family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/index.html" title="Cortex-M0+ Device Generic Users Guide"/>
<description>
The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
- upward compatibility with the rest of the Cortex-M processor family.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM0P.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM0P">
<processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h" define="ARMCM0P"/>
</device>
<device Dname="ARMCM0P_MPU">
<processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h" define="ARMCM0P_MPU"/>
</device>
</family>
<!-- ****************************** Cortex-M1 ****************************** -->
<family Dfamily="ARM Cortex M1" Dvendor="ARM:82">
<!--book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M1 Device Generic Users Guide"/-->
<description>
The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA.
The ARM Cortex-M1 processor implements the ARMv6-M architecture profile.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM1">
<processor Dcore="Cortex-M1" DcoreVersion="r1p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM1/Include/ARMCM1.h" define="ARMCM1"/>
</device>
</family>
<!-- ****************************** Cortex-M3 ****************************** -->
<family Dfamily="ARM Cortex M3" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/index.html" title="Cortex-M3 Device Generic Users Guide"/>
<description>
The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
- upward compatibility with the rest of the Cortex-M processor family.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM3.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM3">
<processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM3/Include/ARMCM3.h" define="ARMCM3"/>
</device>
</family>
<!-- ****************************** Cortex-M4 ****************************** -->
<family Dfamily="ARM Cortex M4" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/index.html" title="Cortex-M4 Device Generic Users Guide"/>
<description>
The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
- upward compatibility with the rest of the Cortex-M processor family.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM4.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM4">
<processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM4/Include/ARMCM4.h" define="ARMCM4"/>
</device>
<device Dname="ARMCM4_FP">
<processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM4/Include/ARMCM4_FP.h" define="ARMCM4_FP"/>
</device>
</family>
<!-- ****************************** Cortex-M7 ****************************** -->
<family Dfamily="ARM Cortex M7" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646b/index.html" title="Cortex-M7 Device Generic Users Guide"/>
<description>
The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
- upward compatibility with the rest of the Cortex-M processor family.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM7.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM7">
<processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM7/Include/ARMCM7.h" define="ARMCM7"/>
</device>
<device Dname="ARMCM7_SP">
<processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM7/Include/ARMCM7_SP.h" define="ARMCM7_SP"/>
</device>
<device Dname="ARMCM7_DP">
<processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM7/Include/ARMCM7_DP.h" define="ARMCM7_DP"/>
</device>
</family>
<!-- ****************************** Cortex-M23 ********************** -->
<family Dfamily="ARM Cortex M23" Dvendor="ARM:82">
<!--book name="Device/ARM/Documents/??_dgug.pdf" title="?? Device Generic Users Guide"/-->
<description>
The Arm Cortex-M23 is based on the Armv8-M baseline architecture.
It is the smallest and most energy efficient Arm processor with Arm TrustZone technology.
Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM23.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/>
<memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM23">
<processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM23/Include/ARMCM23.h" define="ARMCM23"/>
</device>
<device Dname="ARMCM23_TZ">
<processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM23/Include/ARMCM23_TZ.h" define="ARMCM23_TZ"/>
</device>
</family>
<!-- ****************************** Cortex-M33 ****************************** -->
<family Dfamily="ARM Cortex M33" Dvendor="ARM:82">
<!--book name="Device/ARM/Documents/??_dgug.pdf" title="?? Device Generic Users Guide"/-->
<description>
The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller
class processor based on the Armv8-M mainline architecture with Arm TrustZone security.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM33.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/>
<memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM33">
<processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
no DSP Instructions, no Floating Point Unit, no TrustZone
</description>
<compile header="Device/ARM/ARMCM33/Include/ARMCM33.h" define="ARMCM33"/>
</device>
<device Dname="ARMCM33_TZ">
<processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
no DSP Instructions, no Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMCM33/Include/ARMCM33_TZ.h" define="ARMCM33_TZ"/>
</device>
<device Dname="ARMCM33_DSP_FP">
<processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
DSP Instructions, Single Precision Floating Point Unit, no TrustZone
</description>
<compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h" define="ARMCM33_DSP_FP"/>
</device>
<device Dname="ARMCM33_DSP_FP_TZ">
<processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
DSP Instructions, Single Precision Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h" define="ARMCM33_DSP_FP_TZ"/>
</device>
</family>
<!-- ****************************** ARMSC000 ****************************** -->
<family Dfamily="ARM SC000" Dvendor="ARM:82">
<description>
The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
</description>
<!-- debug svd="Device/ARM/SVD/ARMSC000.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMSC000">
<processor Dcore="SC000" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMSC000/Include/ARMSC000.h" define="ARMSC000"/>
</device>
</family>
<!-- ****************************** ARMSC300 ****************************** -->
<family Dfamily="ARM SC300" Dvendor="ARM:82">
<description>
The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
</description>
<!-- debug svd="Device/ARM/SVD/ARMSC300.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMSC300">
<processor Dcore="SC300" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMSC300/Include/ARMSC300.h" define="ARMSC300"/>
</device>
</family>
<!-- ****************************** ARMv8-M Baseline ********************** -->
<family Dfamily="ARMv8-M Baseline" Dvendor="ARM:82">
<!--book name="Device/ARM/Documents/ARMv8MBL_dgug.pdf" title="ARMv8MBL Device Generic Users Guide"/-->
<description>
Armv8-M Baseline based device with TrustZone
</description>
<!-- debug svd="Device/ARM/SVD/ARMv8MBL.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/>
<memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMv8MBL">
<processor Dcore="ARMV8MBL" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMv8MBL/Include/ARMv8MBL.h" define="ARMv8MBL"/>
</device>
</family>
<!-- ****************************** ARMv8-M Mainline ****************************** -->
<family Dfamily="ARMv8-M Mainline" Dvendor="ARM:82">
<!--book name="Device/ARM/Documents/ARMv8MML_dgug.pdf" title="ARMv8MML Device Generic Users Guide"/-->
<description>
Armv8-M Mainline based device with TrustZone
</description>
<!-- debug svd="Device/ARM/SVD/ARMv8MML.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/>
<memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMv8MML">
<processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
no DSP Instructions, no Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMv8MML/Include/ARMv8MML.h" define="ARMv8MML"/>
</device>
<device Dname="ARMv8MML_DSP">
<processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
DSP Instructions, no Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h" define="ARMv8MML_DSP"/>
</device>
<device Dname="ARMv8MML_SP">
<processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
no DSP Instructions, Single Precision Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h" define="ARMv8MML_SP"/>
</device>
<device Dname="ARMv8MML_DSP_SP">
<processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
DSP Instructions, Single Precision Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h" define="ARMv8MML_DSP_SP"/>
</device>
<device Dname="ARMv8MML_DP">
<processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
no DSP Instructions, Double Precision Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h" define="ARMv8MML_DP"/>
</device>
<device Dname="ARMv8MML_DSP_DP">
<processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
DSP Instructions, Double Precision Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h" define="ARMv8MML_DSP_DP"/>
</device>
</family>
<!-- ****************************** Cortex-A5 ****************************** -->
<family Dfamily="ARM Cortex A5" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/index.html" title="Cortex-A5 Technical Reference Manual"/>
<description>
The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full
virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit
Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family.
</description>
<memory id="IROM1" start="0x80000000" size="0x00200000" startup="1" default="1"/>
<memory id="IRAM1" start="0x80200000" size="0x00200000" init ="0" default="1"/>
<device Dname="ARMCA5">
<processor Dcore="Cortex-A5" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
<compile header="Device/ARM/ARMCA5/Include/ARMCA5.h" define="ARMCA5"/>
</device>
</family>
<!-- ****************************** Cortex-A7 ****************************** -->
<family Dfamily="ARM Cortex A7" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html" title="Cortex-A7 MPCore Technical Reference Manual"/>
<description>
The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture.
The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem,
an optional integrated GIC, and an optional L2 cache controller.
</description>
<memory id="IROM1" start="0x80000000" size="0x00200000" startup="1" default="1"/>
<memory id="IRAM1" start="0x80200000" size="0x00200000" init ="0" default="1"/>
<device Dname="ARMCA7">
<processor Dcore="Cortex-A7" DcoreVersion="r0p5" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
<compile header="Device/ARM/ARMCA7/Include/ARMCA7.h" define="ARMCA7"/>
</device>
</family>
<!-- ****************************** Cortex-A9 ****************************** -->
<family Dfamily="ARM Cortex A9" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/index.html" title="Cortex-A9 Technical Reference Manual"/>
<description>
The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions,
and 8-bit Java bytecodes in Jazelle state.
</description>
<memory id="IROM1" start="0x80000000" size="0x00200000" startup="1" default="1"/>
<memory id="IRAM1" start="0x80200000" size="0x00200000" init ="0" default="1"/>
<device Dname="ARMCA9">
<processor Dcore="Cortex-A9" DcoreVersion="r4p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
<compile header="Device/ARM/ARMCA9/Include/ARMCA9.h" define="ARMCA9"/>
</device>
</family>
</devices>
<apis>
<!-- CMSIS Device API -->
<api Cclass="Device" Cgroup="IRQ Controller" Capiversion="1.0.0" exclusive="1">
<description>Device interrupt controller interface</description>
<files>
<file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
</files>
</api>
<api Cclass="Device" Cgroup="OS Tick" Capiversion="1.0.1" exclusive="1">
<description>RTOS Kernel system tick timer interface</description>
<files>
<file category="header" name="CMSIS/RTOS2/Include/os_tick.h"/>
</files>
</api>
<!-- CMSIS-RTOS API -->
<api Cclass="CMSIS" Cgroup="RTOS" Capiversion="1.0.0" exclusive="1">
<description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
<files>
<file category="doc" name="CMSIS/Documentation/RTOS/html/index.html"/>
</files>
</api>
<api Cclass="CMSIS" Cgroup="RTOS2" Capiversion="2.1.3" exclusive="1">
<description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
<files>
<file category="doc" name="CMSIS/Documentation/RTOS2/html/index.html"/>
<file category="header" name="CMSIS/RTOS2/Include/cmsis_os2.h"/>
</files>
</api>
<!-- CMSIS Driver API -->
<api Cclass="CMSIS Driver" Cgroup="USART" Capiversion="2.3.0" exclusive="0">
<description>USART Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__usart__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_USART.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="SPI" Capiversion="2.2.0" exclusive="0">
<description>SPI Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__spi__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_SPI.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="SAI" Capiversion="1.1.0" exclusive="0">
<description>SAI Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__sai__interface__gr.html"/>
<file category="header" name="CMSIS/Driver/Include/Driver_SAI.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.3.0" exclusive="0">
<description>I2C Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__i2c__interface__gr.html"/>
<file category="header" name="CMSIS/Driver/Include/Driver_I2C.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="CAN" Capiversion="1.2.0" exclusive="0">
<description>CAN Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__can__interface__gr.html"/>
<file category="header" name="CMSIS/Driver/Include/Driver_CAN.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="Flash" Capiversion="2.2.0" exclusive="0">
<description>Flash Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__flash__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_Flash.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="MCI" Capiversion="2.3.0" exclusive="0">
<description>MCI Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__mci__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_MCI.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="NAND" Capiversion="2.3.0" exclusive="0">
<description>NAND Flash Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__nand__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_NAND.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="Ethernet" Capiversion="2.1.0" exclusive="0">
<description>Ethernet MAC and PHY Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
<file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="Ethernet MAC" Capiversion="2.1.0" exclusive="0">
<description>Ethernet MAC Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__mac__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="Ethernet PHY" Capiversion="2.1.0" exclusive="0">
<description>Ethernet PHY Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__phy__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="USB Device" Capiversion="2.2.0" exclusive="0">
<description>USB Device Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__usbd__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_USBD.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="USB Host" Capiversion="2.2.0" exclusive="0">
<description>USB Host Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__usbh__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_USBH.h" />
</files>
</api>
</apis>
<!-- conditions are dependency rules that can apply to a component or an individual file -->
<conditions>
<!-- compiler -->
<condition id="ARMCC6">
<accept Tcompiler="ARMCC" Toptions="AC6"/>
<accept Tcompiler="ARMCC" Toptions="AC6LTO"/>
</condition>
<condition id="ARMCC5">
<require Tcompiler="ARMCC" Toptions="AC5"/>
</condition>
<condition id="ARMCC">
<require Tcompiler="ARMCC"/>
</condition>
<condition id="GCC">
<require Tcompiler="GCC"/>
</condition>
<condition id="IAR">
<require Tcompiler="IAR"/>
</condition>
<condition id="ARMCC GCC">
<accept Tcompiler="ARMCC"/>
<accept Tcompiler="GCC"/>
</condition>
<condition id="ARMCC GCC IAR">
<accept Tcompiler="ARMCC"/>
<accept Tcompiler="GCC"/>
<accept Tcompiler="IAR"/>
</condition>
<!-- Arm architecture -->
<condition id="ARMv6-M Device">
<description>Armv6-M architecture based device</description>
<accept Dcore="Cortex-M0"/>
<accept Dcore="Cortex-M1"/>
<accept Dcore="Cortex-M0+"/>
<accept Dcore="SC000"/>
</condition>
<condition id="ARMv7-M Device">
<description>Armv7-M architecture based device</description>
<accept Dcore="Cortex-M3"/>
<accept Dcore="Cortex-M4"/>
<accept Dcore="Cortex-M7"/>
<accept Dcore="SC300"/>
</condition>
<condition id="ARMv8-M Device">
<description>Armv8-M architecture based device</description>
<accept Dcore="ARMV8MBL"/>
<accept Dcore="ARMV8MML"/>
<accept Dcore="Cortex-M23"/>
<accept Dcore="Cortex-M33"/>
</condition>
<condition id="ARMv8-M TZ Device">
<description>Armv8-M architecture based device with TrustZone</description>
<require condition="ARMv8-M Device"/>
<require Dtz="TZ"/>
</condition>
<condition id="ARMv6_7-M Device">
<description>Armv6_7-M architecture based device</description>
<accept condition="ARMv6-M Device"/>
<accept condition="ARMv7-M Device"/>
</condition>
<condition id="ARMv6_7_8-M Device">
<description>Armv6_7_8-M architecture based device</description>
<accept condition="ARMv6-M Device"/>
<accept condition="ARMv7-M Device"/>
<accept condition="ARMv8-M Device"/>
</condition>
<condition id="ARMv7-A Device">
<description>Armv7-A architecture based device</description>
<accept Dcore="Cortex-A5"/>
<accept Dcore="Cortex-A7"/>
<accept Dcore="Cortex-A9"/>
</condition>
<!-- ARM core -->
<condition id="CM0">
<description>Cortex-M0 or Cortex-M0+ or SC000 processor based device</description>
<accept Dcore="Cortex-M0"/>
<accept Dcore="Cortex-M0+"/>
<accept Dcore="SC000"/>
</condition>
<condition id="CM1">
<description>Cortex-M1</description>
<require Dcore="Cortex-M1"/>
</condition>
<condition id="CM3">
<description>Cortex-M3 or SC300 processor based device</description>
<accept Dcore="Cortex-M3"/>
<accept Dcore="SC300"/>
</condition>
<condition id="CM4">
<description>Cortex-M4 processor based device</description>
<require Dcore="Cortex-M4" Dfpu="NO_FPU"/>
</condition>
<condition id="CM4_FP">
<description>Cortex-M4 processor based device using Floating Point Unit</description>
<accept Dcore="Cortex-M4" Dfpu="FPU"/>
<accept Dcore="Cortex-M4" Dfpu="SP_FPU"/>
<accept Dcore="Cortex-M4" Dfpu="DP_FPU"/>
</condition>
<condition id="CM7">
<description>Cortex-M7 processor based device</description>
<require Dcore="Cortex-M7" Dfpu="NO_FPU"/>
</condition>
<condition id="CM7_FP">
<description>Cortex-M7 processor based device using Floating Point Unit</description>
<accept Dcore="Cortex-M7" Dfpu="SP_FPU"/>
<accept Dcore="Cortex-M7" Dfpu="DP_FPU"/>
</condition>
<condition id="CM7_SP">
<description>Cortex-M7 processor based device using Floating Point Unit (SP)</description>
<require Dcore="Cortex-M7" Dfpu="SP_FPU"/>
</condition>
<condition id="CM7_DP">
<description>Cortex-M7 processor based device using Floating Point Unit (DP)</description>
<require Dcore="Cortex-M7" Dfpu="DP_FPU"/>
</condition>
<condition id="CM23">
<description>Cortex-M23 processor based device</description>
<require Dcore="Cortex-M23"/>
</condition>
<condition id="CM33">
<description>Cortex-M33 processor based device</description>
<require Dcore="Cortex-M33" Dfpu="NO_FPU"/>
</condition>
<condition id="CM33_FP">
<description>Cortex-M33 processor based device using Floating Point Unit</description>
<require Dcore="Cortex-M33" Dfpu="SP_FPU"/>
</condition>
<condition id="ARMv8MBL">
<description>Armv8-M Baseline processor based device</description>
<require Dcore="ARMV8MBL"/>
</condition>
<condition id="ARMv8MML">
<description>Armv8-M Mainline processor based device</description>
<require Dcore="ARMV8MML" Dfpu="NO_FPU"/>
</condition>
<condition id="ARMv8MML_FP">
<description>Armv8-M Mainline processor based device using Floating Point Unit</description>
<accept Dcore="ARMV8MML" Dfpu="SP_FPU"/>
<accept Dcore="ARMV8MML" Dfpu="DP_FPU"/>
</condition>
<condition id="CM33_NODSP_NOFPU">
<description>CM33, no DSP, no FPU</description>
<require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
</condition>
<condition id="CM33_DSP_NOFPU">
<description>CM33, DSP, no FPU</description>
<require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="NO_FPU"/>
</condition>
<condition id="CM33_NODSP_SP">
<description>CM33, no DSP, SP FPU</description>
<require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
</condition>
<condition id="CM33_DSP_SP">
<description>CM33, DSP, SP FPU</description>
<require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="SP_FPU"/>
</condition>
<condition id="ARMv8MML_NODSP_NOFPU">
<description>Armv8-M Mainline, no DSP, no FPU</description>
<require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
</condition>
<condition id="ARMv8MML_DSP_NOFPU">
<description>Armv8-M Mainline, DSP, no FPU</description>
<require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="NO_FPU"/>
</condition>
<condition id="ARMv8MML_NODSP_SP">
<description>Armv8-M Mainline, no DSP, SP FPU</description>
<require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
</condition>
<condition id="ARMv8MML_DSP_SP">
<description>Armv8-M Mainline, DSP, SP FPU</description>
<require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="SP_FPU"/>
</condition>
<condition id="CA5_CA9">
<description>Cortex-A5 or Cortex-A9 processor based device</description>
<accept Dcore="Cortex-A5"/>
<accept Dcore="Cortex-A9"/>
</condition>
<condition id="CA7">
<description>Cortex-A7 processor based device</description>
<accept Dcore="Cortex-A7"/>
</condition>
<!-- ARMCC compiler -->
<condition id="CA_ARMCC5">
<description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 5</description>
<require condition="ARMv7-A Device"/>
<require condition="ARMCC5"/>
</condition>
<condition id="CA_ARMCC6">
<description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 6</description>
<require condition="ARMv7-A Device"/>
<require condition="ARMCC6"/>
</condition>
<condition id="CM0_ARMCC">
<description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler</description>
<require condition="CM0"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM0_LE_ARMCC">
<description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the Arm Compiler</description>
<require condition="CM0_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM0_BE_ARMCC">
<description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the Arm Compiler</description>
<require condition="CM0_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="CM1_ARMCC">
<description>Cortex-M1 based device for the Arm Compiler</description>
<require condition="CM1"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM1_LE_ARMCC">
<description>Cortex-M1 based device in little endian mode for the Arm Compiler</description>
<require condition="CM1_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM1_BE_ARMCC">
<description>Cortex-M1 based device in big endian mode for the Arm Compiler</description>
<require condition="CM1_ARMCC"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="CM3_ARMCC">
<description>Cortex-M3 or SC300 processor based device for the Arm Compiler</description>
<require condition="CM3"/>
<require Tcompiler="ARMCC"/>
</condition>
<condition id="CM3_LE_ARMCC">
<description>Cortex-M3 or SC300 processor based device in little endian mode for the Arm Compiler</description>
<require condition="CM3_ARMCC"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="CM3_BE_ARMCC">