Should user mode counter CSRs be accessible / exist?

[rmn30]

RISC-V defines machine-mode mcycle[h], minstret[h] CSRs and memory-mapped mtime[h]. On CHERIoT the first two of these are accessible RW when PCC has Access System Registers permission and read-only when it doesn't. RISC-V also defines user-mode views of these CSRs as cycle[h], time[h] and instret[h]. These latter are allowed in the ASR allow list but aren't actually usable because CHERIoT has no user mode, therefore the Sail acts as though they don't exist. Ibex seems to match this behaviour.

There are a couple of reasons it would be useful to have these user-mode aliases even though we have no user mode:

1. The assembly aliases rdcycle, rdtime and rdinstret are defined to use them and it's a bit confusing that they don't work. In fact I've seen instance of library code assuming they exist.
2. mtime is memory mapped and it would be nice to have a CSR version. On the other hand we get more control over access using capabilities.

Maybe we should add support? See also #22 for more consideration.